An active quenching circuit in 0.35 μm bipolar complementary metal oxide semiconductor (BiCMOS) technology with a high quenching slew rate is introduced. Quenching transients of an integrated single-photon avalanche diode (SPAD) measured by means of an integrated mini-pad are shown. An NPN transistor as quenching switch enables an active quenching time of 350 ps from an excess bias voltage of 6.6 V and a quenching slew rate of 15 V/ns. Active resetting of the SPAD can be achieved in 550 ps. The power consumption of the BiCMOS quenching circuit is 8.6 mW at 40 Mcounts/s and 3 mW in the idle state.
We report on the progress of our efforts to apply silicon nitride photonic integrated circuits (PIC) to the miniaturization of optical coherence tomography (OCT) with the goal of facilitating its widespread use in ophthalmology at the point of care. In particular, we highlight the design and optical characterization of photonic building blocks allowing the realization of a silicon nitride PIC-based multi-channel swept-source OCT system in the 1060 nm wavelength region. Apart from waveguide structures, these building blocks include 3D-printed microlenses on the PIC end facets for efficient light coupling to and from the PIC.
This work presents a highly sensitive hybrid-integrated optical receiver with a custom designed linear transimpedance amplifier (TIA). The choice of the circuit and diode technology, considering the impact of process parameters on the optical sensitivity and the input referred noise current, are elaborated. The TIA has been designed in a 55-nm complementary metal oxide semiconductor process and was combined with a commercial InGaAs/InP PIN-diode. Measurements resulted in a transimpedance of 9.2 kΩ and a bandwidth of 1.4 GHz. The optical sensitivity of the hybrid receiver is −27.45 dBm for 2 Gbps, with a wavelength of 1550 nm and a bit error rate of 10 − 9. The input referred root mean square (RMS) noise current results in 110 nA. The fabricated chip has an area of 410 μm × 410 μm and a power consumption of 31 mW at a 1 V supply voltage. The performance of the designed TIA is able to match other designs used in high sensitivity applications such as continuous variable quantum key distribution or optical wireless communication, while consuming significantly less power and having a smaller chip area.
We present a miniaturized optical coherence tomography (OCT) setup based on photonic integrated circuits (PIC) for the 850 nm range. We designed a 512-channel arrayed waveguide grating (AWG) on a PIC for spectral domain OCT (SD-OCT) that is co-integrated with PIN-photodiodes and analog-to-digital-converters on one single chip. This image sensor is combined with all the necessary electronics to act as a camera. It is integrated into a fiber-based OCT system, achieving a sensitivity of >80dB and various samples are imaged. This optoelectronic system will allow building small and cost-effective OCT systems to monitor retinal diseases.
A highly sensitive monolithic optical receiver, applicable in optical fiber and wireless communication is presented. The proposed chip is capable of processing data rates of up to 10 Mb / s and offers compatibility to standard CMOS logic by creating full 3.3-V output swing. The photodetector of the system is carried out as a large-area fully integrated avalanche photodiode with a diameter of 800 μm and a high responsivity to red light with a wavelength of 675 nm. The receiver features pseudo differential signal processing with offset cancellation feedback to achieve desensitization to background light irradiation usually appearing with optical wireless communication. Additionally, common-mode feedback was implemented to prevent pulse width distorted output signals. Measurements at 2.5, 5, and 10 Mb / s reveal high sensitivities of −50.4, −47.65, and −42.7 dBm, respectively, for BER < 10 − 9 in dark conditions. For the design, a 0.35-μm CMOS process was chosen.
The use of a physical guard ring in CMOS single-photon avalanche diodes (SPADs) based on n + /(deep)p-well and p + /(deep)n-well structures is a common solution to control the electric field of the SPADs periphery and prevent the premature lateral breakdown. However, this leads to a decrease of the detection efficiency, i.e., the fill-factor, especially when the SPADs size is reduced. Our paper presents an experimental and simulation study on replacing the physical guard ring by a virtual guard ring to improve the fill-factor and the scalability of a n + / p-well SPAD implemented in 0.35-μm pin-photodiode CMOS technology. Accordingly, the optimization of the virtual guard ring and its superiority at downscaling are discussed, and the SPAD scalability in size with respect to the fill-factor is quantified in this technology.
Experimental demonstration of a quantum random number generator based on one single-photon avalanche diode (SPAD) detector, a T / ( T − t ) pulse-shaped laser, and an field-programmable gate array (FPGA) acquisition module is presented. An integrated laser driver drives an external laser diode at 670 nm wavelength, whereas the SPAD with a photon detection probability of 18.5% is integrated together with an active quenching-resetting circuit. The SPAD detector generates counts for the interarrival time (IAT) measurement system implemented in an FPGA, where the change of the IATs between consecutive pulses is used to derive a random bit stream. It is shown how the application of a pulse-shaped laser driver can increase the performance of the system as compared to the continuous-wave operation of the laser diode to achieve the maximum generation rate of 5 Mbps while using a single SPAD. The generated numbers pass all randomness tests of the National Institute of Standards and Technology (NIST), Dieharder, and ENT test (pseudorandom number sequence test) suits.
A monolithic optical receiver containing four single-photon avalanche diodes (SPADs) fabricated in 0.35-μm high-voltage (HV) CMOS is introduced and compared with two 4-SPAD receivers realized in pin-photodiode CMOS belonging to the same process family. This HV-CMOS SPAD receiver achieves sensitivities of −55.1 dBm at 50 Mbit / s and −52.0 dBm at 100 Mbit / s, both with digital processing, a bit error rate (BER) of 2 × 10 − 3, and return-to-zero coding using a wavelength of 642 nm. Also at 143 Mbit / s, this BER is achievable. This receiver is especially interesting for applications in which low light intensities can be expected, such as quantum key distribution, optical communications from deep space, and visible light communication for short-range consumer applications.
We present an active pixel for a spectral domain optical coherence tomography sensor on a chip, where optical components are realized in a photonic layer and monolithically integrated with the electronics, whereby light is brought to the pixels using waveguides. The core of the pixel is an amplifier with capacitive feedback (so-called capacitive transimpedance amplifier), apart from that, a correlated double sampling circuit is implemented within the pixel. The proposed active pixel is based on a PIN photodiode and fabricated in 0.35-μm high-voltage CMOS technology. We use three different epitaxial starting material thicknesses (20, 30, and 40 μm) in order to find the device with best performance. The pixel is optimized for high efficiency in a spectral range between 800 and 900 nm. We explain advantages in the spectral responsivity and crosstalk of this pixel over conventional p / n photodiode-based pixels in standard CMOS processes and over the pinned photodiode-based pixel. We also present measured pixel parameters and give comparison with prior work.
We investigate single-photon avalanche diodes with a thick absorption zone leading to a high photon detection probability in the near-infrared spectrum, e.g., to 27.9% at 850 nm. Furthermore, modulation doping for tuning the breakdown voltage in single-photon avalanche diodes is used. Modulation doping allows for reduction of the effective doping in the structure during the design phase without process modifications. We compare a modulation doped version with a single-photon avalanche diode not using this technique. We prove that both versions are operational. The modulation doped version shows a reduced dark count rate and afterpulsing probability at the cost of a reduced photon detection probability.
A fully integrated single-photon avalanche diode (SPAD) using a high-voltage quenching circuit fabricated in a 0.35-μm CMOS process is proposed. The quenching circuit features a quenching voltage of 9.9 V, which is three times the nominal supply voltage to increase the photon detection probability (PDP). To prove the quenching performance, the circuit has been integrated together with a large-area SPAD having an active diameter of 90 μm. Experimental verification shows a maximum PDP of 67.8% at 9.9 V excess bias at a wavelength of 642 nm.
In this paper we present the size reduction of a 160-channel, 50-GHz Si3N4 based AWG-spectrometer. The spectrometer was designed for TM-polarized light with a central wavelength of 850 nm applying our proprietary “AWG-Parameters” tool. For the simulations of AWG layout, the PHASAR photonics tool from Optiwave was used. The simulated results show satisfying optical properties of the designed AWG-spectrometer. However, such high-channel count AWG features large size. To solve this problem we designed a special taper enabling the reduction of AWG structure by about 15%, while keeping the same optical properties. The technological verification of both AWG designs is also presented.
We demonstrate the automatic thermal alignment of photonic components within an integrated optical switch. The WDM optical switch involves switching elements, wavelength de-multiplexers, interleavers and monitors each one needing independent control. Our system manages rerouting of channels coming from four different directions, each carrying 12, 200GHz spaced, wavelengths into eight add/drop ports. The integrated device includes 12 interleavers, which can act either as optical de-interleavers to split the optical signal into odd and even channels or as optical interleavers that recombine the odd and even channels coming from the switching matrix. Integrated Ge photodiodes are placed in key positions within the photonic integrated circuit (PIC) are serve for monitoring. An electronic integrated circuit (EIC) drives the photonic elements by means of dedicated heating circuits (824 on-board heater control cells, 768 for the switching elements and 56 for the interleavers and the mux/de-mux) and reads out the Ge diodes photocurrent through TIAs. We applied a stochastic optimization algorithm to align the spectral response of the interleavers to the ITU grid. We exploit the thermo-optic effect to shift the interleavers pass-band in a desired spectral position. The interleavers are provided with dedicated metallic heaters that can be operated in order to tune the interleaver response, which is typically misaligned due to fabrication inaccuracies. The experimental setup is made of a tunable laser coupled with one input port of optical switch. The optimization algorithm is implemented via a software to drive the EIC till finding the best heating configuration (on the two branches of the interleaver) on the basis of the monitor diode-feedback. This way, the even and odd wavelengths input in the interleaver are directed toward the wanted lines within the switching matrix. Our method has been used for aligning the micro-ring based switching elements in the PIC as well. In that case, the integrated Ge photodiodes have been used to align the photonic components in the PIC in order to enable different pathways for the routing or the broadcasting operation of the optical switch. With no bias applied to the heaters of the switching elements, the optical signal is expected to be maximum at the through port. When the micro-ring heaters are biased, the feedback controller finds the best set of heating values that minimize the optical power at the through port of the switching node. This way, the optical signal is coupled in the drop port and the node is enabled for switching. The algorithm, implemented in LabVIEW, converges over multiple instances and it is robust against stagnation. This work aims at enabling the automatic reconfiguration/restoration of the whole WDW optical switch.
The excess noise of avalanche photodiodes (APDs) integrated in a high-voltage (HV) CMOS process and in a pin-photodiode CMOS process, both with 0.35-μm structure sizes, is described. A precise excess noise measurement technique is applied using a laser source, a spectrum analyzer, a voltage source, a current meter, a cheap transimpedance amplifier, and a personal computer with a MATLAB program. In addition, usage for on-wafer measurements is demonstrated. The measurement technique is verified with a low excess noise APD as a reference device with known ratio k = 0.01 of the impact ionization coefficients. The k-factor of an APD developed in HV CMOS is determined more accurately than known before. In addition, it is shown that the excess noise of the pin-photodiode CMOS APD depends on the optical power for avalanche gains above 35 and that modulation doping can suppress this power dependence. Modulation doping, however, increases the excess noise.
Optimizing avalanche photodiodes (APDs) in standard complementary metal–oxide–semiconductor (CMOS) processes is challenging due to fixed doping concentrations of the available wells. A speed-improved APD in pin photodiode CMOS technology for high-sensitivity and high-speed applications using a lateral well modulation-doping technique is presented. The increased operating voltage of the presented device leads to a −3-dB bandwidth of 2.30 GHz with a multiplication factor of 20 for 1-μW optical power. This corresponds to a responsivity of 7.40 A/W. A multiplication factor of 44,500 was measured at 10-nW optical power. The thick absorption zone leads to an unamplified quantum efficiency of 72.2% at 635-nm wavelength.
We present the first optoelectronic integrated bipolar complementary metal oxide semiconductor (BiCMOS) receiver chip with an avalanche photodiode (APD). A large 200-μm-diameter APD connected to a high-speed transimpedance amplifier designed for a 2-Gbps optical wireless communication system is proposed. The complete chip was realized in a 0.35-μm silicon BiCMOS technology. Due to the thick intrinsic zone and multiplication gain, the responsivity of the APD reaches a value of up to 120 A/W for a wavelength of 675 nm. Furthermore, the capacitance of the APD is <500 fF for reverse bias voltages above 18 V. The receiver has a supply voltage of 3.3 V with a current consumption of 76 mA. The delivered 50-Ω single-ended output swing is 550 mVpp and the overall transimpedance is 260 kΩ with 1.02-GHz bandwidth. The achieved data rate is 2 Gbps with a sensitivity of −30.3 dBm at a bit error rate <10−9.
A monolithically integrated optical receiver in 0.6 μm bipolar complementary metal oxide semiconductor (BiCMOS) technology with 45 channels, each working at a data rate of 3.125 Gbit/s, is described. The optical receiver uses integrated pin photodiodes with a diameter of 90 μm. This parallel optical silicon receiver is capable of operating at 100°C. The parallel optical receiver consumes less than 950 mW in total and each of its channels achieve an optical sensitivity of −17.5 dBm at 850 nm wavelength and a bit error ratio of 10−9.
An avalanche photodiode (APD) fabricated in 0.35 μm high-voltage complementary metal-oxide semiconductor (CMOS) technology, which was originally optimized for linear mode applications, is characterized in Geiger mode operation. This work shows that the used design concept is also suitable for single-photon detection applications and achieves a photon detection efficiency of 22.1% at 785 nm due to a thick detection zone and 3.5 V excess bias. At this operation point, the single-photon APD achieves good results regarding afterpulsing probability (3.4%) and dark count rate (46 kHz) with respect to the large active diameter of 86 μm.
A pn-junction photodiode with a bandwidth in the GHz range is presented. This photodiode is fabricated in a standard 0.35‐μm high-voltage CMOS process with deep n-wells which can isolate negative substrate potentials down to −100 V from the MOS transistors. This photodiode can, therefore, be implemented together with circuits on the same chip. At a reverse bias voltage of −90 V, a bandwidth of 1.2 GHz was measured for 670-nm light. The breakdown voltage of this photodiode is about −180 V.
A vertical pin photodiode with a thick intrinsic layer is integrated in a 0.5-μm BiCMOS process. The reverse bias of the photodiode can be increased far above the circuit supply voltage, enabling a high-drift velocity. Therefore, a highly efficient and very fast photodiode is achieved. Rise/fall times down to 94 ps/141 ps at a bias of 17 V were measured for a wavelength of 660 nm. The bandwidth was increased from 1.1 GHz at 3 V to 2.9 GHz at 17 V due to the drift enhancement. A quantum efficiency of 85% with a 660-nm light was verified. The technological measures to avoid negative effects on an NPN transistor due to the Kirk effect caused by the low-doped I-layer epitaxy are described. With a high-energy collector implant, the NPN transit frequency is held above 20 GHz. CMOS devices are unaffected. This photodiode is suitable for a wide variety of high-sensitivity optical sensor applications, for optical communications, for fiber-in-the-home applications, and for optical interconnects.
Time-of-flight (TOF) range sensors acquire distances by means of an optical signal delay measurement. As the signal travels at the speed of light, distance resolutions in the subcentimeters range require a time measurement resolution that is in the picoseconds range. However, typical clock synthesizers and digital buffers possess cycle-to-cycle jitter values of up to hundreds of picoseconds, which can potentially have a noticeable impact on the TOF system performances. In this publication, we investigate the influence of two common types of cycle-to-cycle jitter distributions on the measured distance. This includes a random Gaussian distribution, which is caused by, e.g., stochastic noise sources, and a discrete jitter distribution, which is found when timing constraints fail in synchronous digital designs. It was demonstrated that a Gaussian cycle-to-cycle jitter has only a negligible impact on the performance of the TOF distance sensors up to a standard deviation of 1 ns of the Gaussian jitter distribution. However, even the discrete cycle-to-cycle jitter investigated in its simplest form lowers the distance precision of the TOF sensor by a factor of 2.86, i.e., the standard deviation increases from 2.9 to 8.3 mm.
This paper summarises our work on modulators for integration, either as a front end approach, or a co-location of custom electronic drivers, approaches that have yielded data rates up to 50Gb/s from a range of device variants. As well as more conventional depletion based devices, we also report photonic crystal cavity based modulators for very low power consumption, as well as other device variants aimed at improving device performance metrics.
Correlation based time-of-flight systems suffer from a temperature dependent distance measurement error induced by the illumination source of the system. A change of the temperature of the illumination source, results in the change of the bandwidth of the used light emitters, which are light emitting diodes (LEDs) most of the time. For typical illumination sources this can result in a drift of the measured distance in the range of ~20 cm, especially during the heat up phase. Due to the change of the bandwidth of the LEDs the shape of the output signal changes as well. In this paper we propose a method to correct this temperature dependent error by investigating this change of the shape of the output signal. Our measurements show, that the presented approach is capable of correcting the temperature dependent error in a large range of operation without the need for additional hardware.
Within this work a single pixel Time-of-Flight (TOF) based range finder is presented. The sensor is fabricated in a 0.35 μm 1P4M CMOS process occupying an area of 45 × 60 μm2 at ~50% fill factor. It takes advantage of the integrated PIN photodiode, representing, to the best knowledge of the author, the first reported TOF device done in this technology with a PIN detector. The measurement results show a standard deviation of 1 cm for a total integration time of 2.2 ms and a received optical power of 10 nW. Furthermore, the maximal measured integration time per single phase step is slightly below 1 ms, being an improvement by the factor of 40 over the previous work using a similar approach. As proven with the measurements, the background light influence on the measured distance can be neglected even if the dc light is by the factor of 600 larger than the modulation signal.
Time-of-Flight (TOF) 3D cameras determine the distance information by means of a propagation delay measurement. The delay value is acquired by correlating the sent and received continuous wave signals in discrete phase delay steps. To reduce the measurement time as well as the resources required for signal processing, the number of phase steps can be decreased. However, such a change results in the arising of a crucial systematic distance dependent distance error. In the present publication we investigate this phase dependent error systematically by means of a fiber based measurement setup. Furthermore, the phase shift is varied with an electrical delay line device rather than by moving an object in front of the camera. This procedure allows investigating the above mentioned phase dependent error isolated from other error sources, as, e.g., the amplitude dependent error. In other publications this error is corrected by means of a look-up table stored in a memory device. In our paper we demonstrate an analytical correction method that dramatically minimizes the demanded memory size. For four phase steps, this approach reduces the error dramatically by 89.4 % to 13.5 mm at a modulation frequency of 12.5 MHz. For 20.0 MHz, a reduction of 86.8 % to 11.5 mm could be achieved.
We report a Germanium lateral pin photodiode integrated with selective epitaxy at the end of silicon waveguide.
A very high optical bandwidth estimated at 120GHz is shown, with internal responsivity as high as 0.8A/W at
1550nm wavelength. Open eye diagram at 40Gb/s was obtained under zero-bias at wavelength of 1.55μm.
We present the state of the art of integrated silicon photodetectors and circuits by concentrating on the progress in the
last decade. Especially three highlights will be presented in more detail.
In this paper a vertical pin-photodiode in a 0.6μm BiCMOS technology, consisting of an n-buried cathode, an n- epi
layer, and a p+ anode will be discussed. The measured responsivities for different wavelengths are 0.33A/W @ 850nm
and 0.46A/W @ 660nm, respectively. Really outstanding is the reached speed of the photodiodes. The -3dB cut-off
frequencies of these 50x50μm2 diodes are up to 2.1GHz @850nm light and up to 3GHz @660nm light, depending on the
reverse bias voltage.
This high performance photodiode allows the competition of pure silicon optoelectronic integrated circuits (OEICs) even
with GaAs OEICs. A silicon OEIC reaches at 2.5Gb/s1 a higher sensitivity than a GaAs OEIC2. It also consumes less
power and a remarkably smaller chip area.
Massive parallel integration of optical receivers enables an extremely high total data rate. A new OEIC consisting of 45
parallel channels with a data rate of 3Gb/s @850nm each allows an overall data rate of 135Gb/s.
Silicon photonics have generated an increasing interest in the recent year, mainly for optical
telecommunications or for optical interconnects in microelectronic circuits. The rationale of silicon photonics
is the reduction of the cost of photonic systems through the integration of photonic components and an IC on a common chip, or in the longer term, the enhancement of IC performance with the introduction of optics inside
a high performance chip.
In order to build a Opto-Electronic Integrated circuit (OEIC), a large European project HELIOS has been
launched two years ago. The objective is to combine a photonic layer with a CMOS circuit by different
innovative means, using microelectronics fabrication processes. High performance generic building blocks
that can be used for a broad range of applications are developed such as WDM sources by III-V/Si
heterogeneous integration, fast Si modulators and Ge or InGaAs detectors, Si passive circuits and specific
packaging. Different scenari for integrating photonic with an electronic chip and the recent advances on the
building blocks of the Helios project are presented.
The presented paper describes a 10 Gbps optical receiver. The transimpedance amplifier (TIA) is realized in standard
0.35 μm SiGe BiCMOS technology. The main novelty of the presented design - investigated in the European
Community project HELIOS - is the hybrid connection of the optical detector. The used Germanium photodetector will
be directly mounted onto the receiver.
A model of the relevant parasitics of the photodetector itself and the novel connection elements (micropads, metal vias
and metal lines) is described. Based on this photodetector model an optical receiver circuit was optimized for maximum
sensitivity at data rates in the range of 10 Gbps.
The design combines a TIA and two limiting amplifier stages followed by a 50 Ω CML-style logic-level output driver.
To minimize power supply noise and substrate noise, a fully differential design is used. A dummy TIA provides a
symmetrical input signal reference and a control loop is used to compensate the offset levels. The TIA is built around a
common-emitter stage and features a feedback resistor of 4.2 Ω. The total transimpedance of the complete receiver
chain is in the range of 275 kΩ. The value of the active feedback resistor can be reduced via an external control voltage
to adapt the design to different overall gain requirements. The two limiting amplifier stages are realized as differential
amplifiers with voltage followers. The output buffer is implemented with cascode differential amplifiers. The output
buffer is capable of driving a differential 50Ω output with a calculated output swing of 800mVp-p.
Simulations show an overall bandwidth of 7.2 GHz. The lower cutoff frequency is below 60 kHz. The equivalent input
noise current is 408 nA. With an estimated total photodiode responsivity of 0.5 A/W this allows a sensitivity of around -
23.1 dBm (BER = 10-9). The device operates from a single 3.3 V power supply and the TIAs and the limiting amplifier
consume 32 mA.
We report on monolithically integrated PIN photodiodes whose responsivity values could be significantly enhanced over
the whole spectral range by the implementation of a Bottom Antireflective Coating (BARC) process module into
austriamicrosystems 0.35μm CMOS as well as high-speed SiGe BiCMOS technologies. The resulting photodiodes
achieve excellent responsivities together with low capacitances and high bandwidths. We processed finger-photodiodes
with interdigitated n+ cathodes, which are especially sensitive at low wavelengths, and photodiodes with full area n+
cathodes on very lightly p-doped start material. We present a method of depositing an antireflective layer directly upon
the Si surface of the photodiode by changing the standard process flow as little as possible. With just one additional mask
alignment and a well controlled etch procedure we manage to remove the thick intermetal oxide and passivation nitride
stack over the photodiodes completely without damaging the Si surface. The following deposition of a CVD Silicon
Nitride BARC layer not only minimizes the reflected fraction of the optical power but also acts as passivation layer for
the photodiodes. Another benefit of BARC processing is the fact that in-wafer and wafer-to-wafer quantum efficiency
variations can be dramatically reduced. In our experiments we deposited BARC layers of different thicknesses that were
optimised for violet, red and infrared light. Responsivity measurements resulted in values as high as R=0.27A/W at
λ=410nm, R=0.53A/W at λ=670nm and R=0.5A/W at λ=840nm.
A double-cathode photodetector (DCP) featuring a buried-finger structure to achieve improved separation efficiency is
presented. The interleaving comb-shaped cathodes are realized with n-buried implants and they are located in the
p-epitaxial layer roughly 1μm below the surface. Based on MEDICI device simulations several layout variations have
been realized in a slightly modified BiCMOS process. Best results are achieved with a finger distance of 12μm and a
finger width of 1μm: separation efficiencies of 50, 67, and 54% and responsivities of 0.23, 0.47, and 0.38A/W were
measured for the optical wavelengths 410nm, 660nm, and 850nm, respectively. All test structures occupy optical active
areas of around 100×100μm2. A maximum 3dB-modulation bandwidth of almost 300MHz was measured, while dark
currents in the picoampere range are typical for these detectors up to a bias voltage of 5V at room temperature. In the
application of a time-of-flight (TOF) distance measurement sensor, the DCP serves as optical detector and correlating
device at the same time. Distance measurements up to 6.2m were performed with a 650nm laser source that emitted an
average optical power of 1mW using rectangular modulation signals at 10MHz. The standard deviation is better than
1cm up to 3.4m for a total measurement time of 20ms per acquired distance point.
We present an improvement of monolithically integrated photodiodes in a p-type substrate of a commercial high-speed 0.35μm SiGe heterojunction bipolar transistor (HBT) BiCMOS technology. These photodetectors (PDs) combine low capacitance with high bandwidth and responsivity. Slight process modifications of the standard HBT process have been introduced in order to decrease leakage currents and enhance reach-through stability of the PDs. These modifications
have been chosen carefully in order not to alter any other transistor parameters as shown in [1]. To enable low capacitances of the PDs very lightly p-doped epitaxially grown layers of different thicknesses over highly p-doped substrates have been investigated. The improvement becomes manifest, e.g. in a bandwidth of 557MHz and a responsivity of 0.19A/W of a finger photodiode at blue light and a reverse bias voltage of 4V in a 10μm cathode digit-spacing configuration. The capacitance of this finger photodiode is 150fF, overtopping the regular PIN photodiode published in [2] for
the same light-sensitive area with a capacitance of 225fF. Results of detectors with interdigitated cathode distances of 5μm, 10μm, 15μm and 30μm are presented over the wide spectrum of technologically significant optical wavelengths from near-infrared to blue and ultraviolet. These detectors fulfil the requirements demanded by photodiode integrated circuits for universal backward compatible optical storage systems.
Within this work a 28 pixels line sensor for distance measurement applications is presented based on the time-of-flight
principle and the double-correlator circuit concept. An on-chip oscillator block generates 15-phase steps of the
fundamental 10 MHz clock with σ = 1.28 %, which is necessary for calculating the triangular correlation function out of
which the distance information is obtained. Measurement results in a range up to 3 m with a standard deviation ≥ 3.5 cm
are achieved. The pixel autonomous background light suppression is capable of managing background illumination
> 100 kLux. A smart bus concept reduces the number of control signals to the pixels and guarantees 80 dB attenuation
from the oscillator signals to the analog differential outputs of the chip. The line sensor was realized in a single-chip
solution embodying the silicon PIN photodiode detectors.
In this work we present experimental results of silicon-only bipolar phototransistors fabricated in a 0.35μm commercial
BiCMOS technology without process modifications. The transistors are characterized over a wide optical spectral range
at 410nm, 675nm, 785nm, and 850nm, providing significantly improved -3dB bandwidths up to 390MHz @ 410nm
light and responsivities of 1.76A/W @ 675nm corresponding to quantum efficiencies of 359% normalized in terms of
the quantum efficiency of a silicon photodiode.
Within this work a new correlating photodetector concept using current carrying photogates for Time-Of-Flight (TOF)
based optical distance measurements is presented. The integrated photodetector consists of a PIN setup with a P+ doped
anode, two N+ doped cathode fingers and a wide low doped intrinsic region in between. Furthermore a resistive
polysilicon photogate is located in between of the readout cathode fingers on top of field oxide. Applying an electrical
modulation signal to this photogate causes a linear potential drop along the resistor as a result of the control current.
Therefore constant electric field is achieved in the photodetector regions below thus effecting photogenerated electrons
to be directed to one or the other cathode, depending on the sign of the field. While positive charges are collected by the
anode below, the modulation signal controls whether photocurrent of incident light is led to readout cathode 1 or 2. Due
to this setup, applied modulation signals cause an optimal potential distribution for efficient correlation of ηsep=80% with
incident optical signals. A responsivity of 0.23A/W {0.21A/W}, a rise time of 19.3ns {18.3ns} and a bandwidth of
f-3dB=22.7MHz {29.6MHz} is measured at 660nm {850nm} together with low dark current of Idark<0.5pA. The capability
of this photodetector is demonstrated at an integrated rangefinder chip in a range of 1.5m-3.5m achieving a standard
deviation of σ<5cm at a white paper target and an optical power of Popt=1.5mW. A comparison of three realized
photodetectors with different shapes of the photogate is done, each with an active area of 100μm×100μm and processed
in 0.6μm BiCMOS.
For various industrial applications contact-less optical 3D distance measurement systems with active illumination are suitable. A new approach for a pixel of such a 3D-camera chip for applications in displacement and 3D-shape measurement is presented here. The distance information is gained by measuring the Time-of-Flight (TOF) of photons transmitted by a modulated light source to a diffuse reflecting object and back to the receiver IC. The receiver is implemented as an opto-electronic integrated circuit (OEIC). It consists of a double-cathode photodetector performing an opto-electronic correlation, a decoupling network and an output low-pass filter on a single silicon chip. The correlation of the received optical signal and the electronic modulation signal enables the determination of the phase-shift between them. The phase-shift is directly proportional to the distance of the object. The measurement time for a single distance measurement is 20 ms for a range up to 6.2 m. The standard deviation up to 3.4 m is better than 1cm for a transmitted optical power of 1.2 mW at a wavelength of 650 nm. The OEIC was fabricated in a slightly modified 0.6 &mgr;m BiCMOS technology with a PIN-photodetector. The photosensitive area of the integrated PIN-photodetector is 120x115 &mgr;m2. A fill factor of ~67% is reached.
Herein we present optical receivers with external large-area photodiode. It is intended as POF receiver for 1.25Gb/s optical fiber-line access networks. Further an overview on high-speed optical receivers with integrated and external detector in CMOS and BiCMOS, as well as in technologies of III-V compounds is provided. This work's receiver circuits are realized in 0.35μm SiGe BiCMOS technology. The first amplifier stage is a two-transistor transimpedance amplifier using a common-emitter and an emitter-follower configuration. The light-sensitive areas of the two receivers presented are 0.25mm2 (squared PIN diode) and 0.5mm2 (circular APD), with a rise time of 0.4ns and 0.7ns, respectively, at 850nm light. A high sensitivity is also required, where the receiver with external PIN diode reaches a sensitivity of -25.9dBm at the optical input using low-cost silicon-based material only.
This paper presents a transimpedance amplifier (TIA) with the logarithmic compression of the input current
signal. The presented TIA has two regions of operation: a linear one for small input current signals and a compression
one for high input currents, that could otherwise saturate the TIA. The measured -3dB bandwidth in
the linear region of operation is 102MHz. The measured maximum input current overdrive is 20.5mA. However,
the maximum of the monotonic compression is approx. 8mA. Using the compression technique we could achieve
low rms equivalent input noise current (~20.2nA) within the measured bandwidth and with approx. 2pF capacitance
at the input. Thus the dynamic range at the input of the TIA is approx. 120dB considering the maximal
current overdrive. The proposed TIA represents the input stage of a optical receiver with integrated differential
50&OHgr; output driver. The optical receiver occupies approx. 1.24mm2 in 0.35 &mgr;m SiGe BiCMOS technology and
consumes 78mA from 5V supply.
This work presents two types of optical receivers with large-diameter photodiodes. Both are optoelectronic integrated circuits (OEICs) realized in 0.6μm BiCMOS Si technology integrating PIN photodiode, transimpedance amplifier (TIA) and output circuit on chip. The two circuits are an optocoupler with a photodiode diameter of 780μm and a rise- and falltime of 5ns and 4.9ns respectively at 850nm light and a plastic optical fiber (POF) receiver with a photodiode diameter of 500μm and upper -3dB cut-off frequencies of 165MHz at 660nm light and 148MHz at 850nm light. The measured rise- and falltime of the POF receiver was 1.78ns and 2.45ns at 660nm light and 1.94ns and 2.5ns at 850ns, respectively. The presented results combine the advantage of easier handling of large-diameter photodiode receivers and high performance.
Contact-less optical distance measurement systems are necessary to obtain 3D-information of an entire scene. To be able to determine depth information of the scene by a sensor without moving parts like e.g. scanner, it is necessary to measure the distance from the camera to an object in every single pixel. A new pixel for such a 3D-camera is presented. The operating principle is based on the time-of-flight (TOF) of laser light from a modulated light source to a diffuse reflecting object and back to the receiver IC. The receiver is implemented as an opto-electronic integrated circuit (OEIC). It consists of a fast, efficient PIN-photodiode having a 3dB bandwidth of about 1.35 GHz, a single-stage transimpedance amplifier and an electronic mixer on a single silicon chip. By correlating the received optical signal and the original electronic modulation signal, the phase-shift between sent and received signal can be determined. By performing correlation with a delayed modulation signal it is possible to eliminate the influence of object reflectivity and background illumination. The measurement time for a single distance measurement is 500μs for a range up to 3.7m. The standard deviation at 2.5m is better than 3cm for a transmitted optical power of 1.44mW at a wavelength of 650nm. The OEIC was fabricated in a slightly modified BiCMOS 0.6μm process. The diameter of the photosensitive area of the integrated PIN-photodiode is 100μm. The effective pixel size is about 220x400μm2. Therefore a fill factor of ~9% is reached.
KEYWORDS: Signal processing, Logic, Sensors, Photodiodes, Image processing, Receivers, Array processing, Digital signal processing, Detection and tracking algorithms, Intelligent sensors
We present a chip, which is suited for applications in data-communication areas as well as in image-processing applications. Through the combination of parallel signal gathering and processing, we save components and we can increase the processing rate. We think thereby on problems like pre processing in camera systems also called "intelligent sensor". The chip has a structure as follows. Every processor element contains an optical detector, a trans-impedance amplifier and a comparator. A digital logic is directly connected to these components. This logic realizes the programmable processing of the signals. Each processor element is connected to its four direct orthogonal neighbours within the processor array. The digital parts consist of a special processor. It realises simple hard-wired image algorithms. As an example for cooperation of the analogue and digital part we have implemented some morphologic operations. Our receiver consists of a 8×8 photodiode array. A data rate of 625 Mbit/s for an average optical power in the range of 25 µW to 500 µW is possible for a bit-error-rate of 10-9 per channel. Signal processing limits the frequency to 200 MHz for a processor element according to simulations. Using an image with a size of 6×6 according to parallel data transfer a data throughput of 7.2 GHz results.
In resent publications we presented PIN photodiodes with a bandwidth of 600MHz implemented in low-cost 0.6μm BiCMOS technology. A new method to increase the response time of these PIN photodiodes is proposed here. This method was applied to design an optical fiber receiver with a maximum possible data rate of 2.5Gbit/s. In addition to the PIN photodiode attached to a transimpedance amplifier it also includes a decision circuit and a 50Ω output driver. The measured bandwidth of the receiver of 1.90GHz is sufficient for 2.5Gbit/s. At an optical wavelength of 660nm, a sensitivity of -17.0dBm was measured. At a supply voltage of 5V, the power consumption of the complete receiver is 171mW, from which the output driver requires 128mW. The overall chip size is 1154μm times 727μm.
We present an optical fiber receiver which includes a monolithically integrated PIN photodiode, a transimpedance amplifier, a decision circuit and a PECL compatible output driver. This low-cost and low-power receiver was fabricated in 0.6μm BiCMOS technology. Only one minor process modification was necessary to implement the PIN photodiodewith a diameter of 150μm. A minimum number of external components is needed for interfacing with standard PECL gates. At a maximum possible data rate of 625Mbit/s, a sensitivity of -22.7dBm was measured at an optical wavelength of 660nm. At a single-supply voltage of 5V, the power consumption of the complete receiver is less than 74mW. The overall chip size is 1763μm times 648μm.
Integrated optical distance measurement systems based on the Time-of-Flight (TOF) principle open up 3D vision for various applications like e.g. inspection systems. The introduced single pixel consists of both, a PIN photodiode and a signal-processing circuit on chip. Due to eye-safety reasons, the optical illumination power is limited (Popt<2mW). For diffuse reflecting objects in distances up to several meters, signal attenuation of about -50dB occurs with 1-inch optics. Therefore high responsivity of the photodiode is required: R=0.36A/W at 660nm. Resolutions of centimeters matter TOF far below 1ns, i.e. the photodiode has to feature high bandwidth (f3dB=1.35GHz). Distance information is gained by correlation between the modulated transmission signal and the run- ime delayed, attenuated received signal. The readout circuit consists of three stages: the first stage is a broadband current amplifier, realised with current mirrors. The correlation is performed in the second stage by a switching mixer. Amplification and smoothing is performed in the third, active integrator stage. The distance information is derived from the output signal by external sampling and simple data processing. A standard deviation of better than 1% (2%) for distances up to 2m (3.7m) is achieved for measurement durations of 10ms. The primary linearity error of less than 6cm is educed by error correction. The pixel has a fill factor of ~10%, including the overall pixel area of ~460µm×170µm and the photodiode with a diameter of 100µm. The chip was realised in a 0.6µm BiCMOS ASIC process.
Optoelectronic integrated circuits (OEICs) offering high bandwidth and high sensitivity as well are needed for the pickups of optical storage systems of the next generation, such as Blu-Ray or HDDVD. High bandwidth is necessary to enable high data transfer rates between the disk and the processing device, and high sensitivity allows to operate at low optical power and to deal with the lower efficiency of the photodiodes for blue light. Two methods will be presented to increase the bandwidth of the OEIC while maintaining high sensitivity. The first approach reduces the parasitic capacitance by placing the feedback resistor in a low-doped region. By this way the parasitic capacitance of the resistor is combined in series with the small depletion-layer capacitance of the low-doped region, which results in a drastically reduced effective capacitance. Using this method the 3dB-frequency of a standard one-stage transimpedance amplifier is increased by 55% from 67MHz to 104MHz. In the second approach the feedback resistor is replaced by a network that consists of two resistive voltage dividers that are coupled via a capacitor. Using such a capacitive-coupled voltage divider (CCVD) the feedback path is split into a low- and a high-frequency path and the effective band-limiting RC-constant is reduced. A bandwidth of 378MHz could be achieved. With a measured transimpedance of 212kΩ this results in a GBW of 80.3THzΩ.
We present a system for direct parallel optical data communication between integrated circuits on neighboured printed circuit boards based on a monolithic integrated CMOS smart pixel array, fibre arrays, and VCSELs. The advantage of our system versus backplane systems is the direct data transfer through the space avoiding planar and area consuming interconnections. The detector chip allows a data rate of 625 Mbit/s per link and is cycled by an optical clock. A simulation of the chip layout showed 260 % more performance versus electrical off-chip interconnects. In principle an 8'8 data transfer is feasible allowing a data rate of 40 Gbit/s. The detector combines an optical receiver array with a digital processor array which executes image processing algorithms. The optical receiver is formed by a PIN photodiode with a diameter of 40 µm, a transimpedance amplifier (TIA) and a decision-making postamplifier. The measured responsivity of the photodiode without antireflection coating is R=0.382 A/W at an optical wavelength of 670 nm. The TIA consists of a CMOS inverter and a PMOS transistor forming the feedback resistor. Together with the postamplifier, formed by a chain of five CMOS inverters and attaining digital CMOS levels, a data rate of 625 Mbit/s is achieved.
Generally, a high-speed optical sensor consists of a photodiode and a transimpedance amplifier. If a large photosensitive area is demanded, the resulting large junction capacitance of the photodiode limits both the bandwidth and the noise behavior of the transimpedance amplifier. Therefore we suggest an innovative approach, which divides the photodiode into four electrically isolated sections. Each of the four-quarter photodiodes is connected to a transimpedance amplifier and their output voltages are combined with a summation amplifier. The capacitance of each of the four-quarter photodiodes is only one fourth of the capacitance of the undivided photodiode, therefore the bandwidth of the innovative optical sensor is 223MHz, which is three times as high as the bandwidth of a transimpedance amplifier with an undivided photodiode. The photo-sensitivity is more than doubled to 75mV/μW.
Future DVD-systems require optical pickup units with high bandwidth and high sensitivity in the red and blue spectral range. OEICs (OptoElectronic Integrated Circuits) use monolithically integrated photodetectors in order to avoid the bond pad capacitances between photodiode and amplifier and to increase the bandwidth compared to discrete or two-chip optical receivers. For this reason, OEICs are a good approach for future DVD-applications.
We introduce a solution that integrates a PIN photodiode and a transimpedance amplifier in a 0.6μm BiCMOS process. The innovative transimpedance amplifier consists of two branches connected via a common current source in order to achieve differential outputs and to double the transimpedance without increasing the offset voltage. The amplifier is optimized for high bandwidth.
The measured results show a -3dB cut-off frequency of 500MHz and a differential transimpedance of 76kΩ. This is 2.2 times the bandwidth and 1.3 times the transimpedance compared to the results presented in the literature. Measurements also show that the OEIC is appropriate for fiber receiver applications at 1.25Gb/s with a record sensitivity of -27.7dBm.
For digital versatile disk (DVD) applications, amplifiers with high bandwidth and high sensitivity in the red spectral range are required. The presented optoelectronic integrated circuit (OEIC) achieves a bandwidth of 265MHz and a transimpedance of 210kΩ due to an advanced feedback network. This is an improvement by a factor of 4 compared to the same amplifier with a simple feedback resistor.
Photodiode structures were integrated in a low cost 0.5 μm silicon BiCMOS process using standard process flow without any technology modification. Rise times of 1.3ns and 1.4ns were measured for wavelengths λ of 660nm and 780nm with a responsivity of 0.23 A/W and 0.14 A/W, respectively. Photodiodes with a high responsivity of 0.42 A/W are reaching a risetime of 4ns for λ = 780nm. Comparable low values for the risetime at 780nm are reported in the literature for integrated photodiodes in standard silicon technologies only with a modification of the epitaxial substrate material. So this photodiodes are suitable for a wide variety of low-cost high-speed optical sensor applications, for optical fiber communication and fiber in home applications.
Currently two very interesting trends in design of optical receivers can be observed. The first is to realize optical receivers in deep-sub-μm CMOS technology and to integrate them in analog-digital systems-on-a-chip (SoC). The second even much more innovative trend is to integrate voltage-up-converters (VUCs) in optoelectronic integrated circuits (OEICs) to increase the bandwidth and data rate, whereby only the chip voltage supply is necessary. The properties of deep-sub-µm CMOS optical receivers and of sub-μm OEICs with respect to current consumption, noise, and chip area will be compared. For both trends a new design each and measured results will be presented. The first example is a burst-mode receiver in digital 0.18μm CMOS technology with sensitivities better than -28 dBm and -22 dBm at data rates of 622Mb/s and 1.25Gb/s, respectively, for a bit error rate of 10-10 each. These values compare to sensitivities of -24.5 dBm and -24.1 dBm, respectively, of a 0.6μm BiCMOS OEIC. For implementation of the burst-mode receiver in an analog-digital SoC, a differential circuit is chosen. Another example is an OEIC in 0.6μm BiCMOS technology with an integrated VUC, which generates a bias voltage of 16V for the integrated photodiode from the chip supply voltage of 5V. Due to the VUC, the data rate for the given technology is increased from 50Mb/s to 1.5Gb/s. The dependence of the receiver sensitivity and of the maximum photocurrent on the VUC clock-frequency will be shown. The VUC-OEIC represents a complete SoC consisting of sensor, analog and digital part. Aspects of substrate noise coupling from the digital part into the photodiode and amplifier are discussed.
The state of the art of silicon optoelectronic integrated circuits (OEICs) is described. It is verified that silicon OEICs achieve both high sensitivities and high bandwidths up to the GHz range. Silicon OEICs,therefore, compete successfully with III/V OEICs for low-cost high-volume applications.Results of advanced monolithically integrated photodiodes available in CMOS and BiCMOS technologies are presented. The technological aspects for the monolithic integration of photodiodes are addressed and the properties of the so-called double photodiode and of the pin photodiode are described. The innovative integrated double photodiode allowing data rates of 622 Mb/s is available in standard silicon technologies without any process modification. For the integration of the pin photodiode allowing data rates of higher than 1 Gb/s usually at least one additional mask is required. It will be shown that the pin photodiode also can be implemented without an additional mask. The second main part of this article covers circuits of optical fiber and interconnect receivers with data rates of up to 1 Gb/s as well as advanced DVD pick-up OEICs with bandwidths of up to 150 MHz. The fiber receivers achieve an effective transimpedance of 45.9 k(Omega) and the sensitivity of this OEIC in a 1.0 micrometers CMOS technology with a data rate of 1 Gb/s is improved by 9 dB compared to that of a published OEIC in a 0.35 micrometers CMOS technolgy.
Novel monolithic optical receivers in 0.8 micrometers standard MOS technology with NRZ data rates in excess of 531 Mb/s at 850 nm are introduced. At 638 nm the data rates are above 622 Mb/s. The innovative integrated double photodiode allowing this high speed without any modification in a CMOS process is described and results for their quantum efficiency and for their transient response are presented. Furthermore the improvement of the sensitivity of the photodiodes and the OEICs by an antireflection coating is discussed. The circuit topology of the OEICs is described. A transimpedance input stage with an active MOS feedback resistor is implemented. Analytical calculations for the bandwidth and for the effective transimpedance of the amplifiers as well as measured results are presented. Finally, an OEIC in a 1.0 micrometers CMOS technology with a polysilicon resistor instead of a MOS feedback resistor and implementing a pin photodiode achieves a data rate of 1 Gb/s for 638 nm. The sensitivity of this OEIC is improved by 9 dB m compared to that of a published OEIC.
Two optoelectronic integrated circuits (OEICs) are presented: a current mirror amplifier for low-offset DVD OEICs and a high-speed amplifier for optical data transmission and optical interconnects. Both OEICs were integrated with PIN photodiodes in a standard 1 micrometers CMOS process on epitaxial wafers. For the DVD OEIC -3 dB- frequencies in excess of 30 MHz and for the high-speed receiver a NRZ data rate of 622 Mbit/s are achieved.
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