Line edge roughness (LER) played more critical- role with the semiconductor manufacturing keep shrinking down to new technology nodes. From our previous study, the larger exposure area gives positive impact to LER performance, as more photons can be captured by photoresist, reducing the randomness of photoacid distribution and make line edge smoother. In this paper, we further investigate the litho process impact factors for LER, including Normalized Image Log-Slope (NILS) and exposure energy. Simulation model was setup on top of experiment data, and further expand to different critical dimension (CD) and pitch conditions.
With the continuous resolution shrinking in cutting edge semiconductor industry such as memory device, on product overlay (OPO) control has become more and more challenging. Reticle heating is a critical impact to OPO when DUV light exposes to the reticle, as the thermal expansion of the reticle induces nanos of overlay error on wafer level which directly impacts device function. Reticle heating control functions has been developed to compensate overlay error in current advanced scanners for normal full reticle, of which one layer mask occupies one reticle. However, the heating effect of Multilayer Reticle (MLR), wherein one reticle consists of multiple mask layers, is less discussed. In this paper, we investigated the reticle heating effect to OPO on MLR, and the methods for MLR heating control is proposed.
Researchers occasionally use a single photomask to create a stacked structure with identical patterns. This method is cost-effective but also challenging for precise overlay control, due to the lack of coupled overlay marks between successive layers. In this paper, an innovative approach has been developed to address this problem. By shifting the exposure field with a specific offset, the outer overlay mark of the previous layer and the inner overlay mark of the current layer are aligned to the same coordinate position, allowing for accurate measurement of the overlay error. The raw overlay measurement values are then modeled using polynomials and compensated during subsequent runs. The effectiveness of this method has been demonstrated with experiment wafers, and PFA (Physical Failure Analysis) result further confirmed its feasibility for achieving precise overlay in such applications.
Inverse lithography technology (ILT) is an emerging computational lithography technique that utilizes advanced mathematical algorithms to optimize the mask pattern based on the desired wafer image. Compared with conventional optical proximity correction (OPC), ILT offers advantages in enhancing process window (PW) and reducing edge placement error (EPE) However, the mask writing time and the complexity of the mask writing process is significantly increased due to the complex mask pattern. The current approach involves Manhattanizing curve features to achieve nearly equivalent image quality on a wafer, but the relationship between the Manhattan levels of ILT and improvements in on-wafer performance has not been fully explored. This paper explores the effects of conventional OPC and Manhattanized ILT on on-wafer image fidelity, with a particular focus on the effectiveness of Manhattanized ILT in improving PW and reducing mask writing time. The study compares conventional OPC and Manhattanized ILT to evaluate their lithography performance across specific hotspot patterns. The findings reveal that Manhattanized ILT significantly enhances PW, while also evaluating the trade-offs between mask writing time and PW improvements. Additionally, this study emphasizes the significance of Manhattanized ILT in enhancing EPE.
In recent years, Inverse Lithography Technology (ILT) has been widely used as a new mask correction technology to further improve the imaging performance in advanced imaging at low-k1 lithography regime. Compared to the conventional Optical Proximity Correction (OPC), ILT enables better process window (PW), edge placement error (EPE) specially for 2D pattern, etc. However, ILT naturally generates more complex, nonrectilinear mask shapes, which is a challenge to accurately characterize mask pattern critical dimensions. Accurate characterization of the written ILT Mask is crucial for tuning the ILT Mask manufacturing process, establishing accurate ILT models and quantitatively evaluating the impact of Mask error on wafer imaging performance. Applying contour-based mask quality characterization instead of traditional gauge-based method for non-rectilinear mask dimensions has been considered as a more reliable solution. In this work, we’ve developed an offline batch contour-based methodology flow. It includes contour extraction from SEM images, contour-layout alignment, SEM contours GDS merge, polygon-based SEM contour GDS analysis, statistics and visualization. Based on this methodology flow, we’ve quantified an ILT Mask which has been manufactured by a Variable Single Beam e-Beam writer. Besides, we’ve explored the impact of mask quality on wafer imaging performance based on a clipped mask contour GDS and ILT model. Combined with simulation data on an ideal mask GDS and actual on wafer imaging data we able to separate mask impact on wafer imaging performance from other process fluctuations.
Inverse Lithography Technology(ILT)has received much attention in recent years due to its outstanding performance in the new technology node development. Compared to conventional OPC technology, the all-angle nature of ILT makes modeling and simulation more challenging. In this study, we introduced a novel ILT modeling method that applies varied-angle gauges to enhance the model accuracy of patterning with a curvilinear mask. Initially, we designed a curvilinear mask pattern and collected the related CDSEM data after mask fabrication and wafer exposure. Subsequently, three kinds of gauge combinations for model calibration were created using gauge numbers of 252 (0°, 90°), 504 (0°, 90°, ±45°), and 1008 (0°, 90°, ±45°, ±30°, ±60°), incorporating different CD information extracted from the CDSEM image contours. Through rigorous model fitting and validation, the calibrated ILT model with all-angle gauges demonstrated superior performance compared to the model calibrated with conventional horizontal and vertical gauges, particularly for low-symmetry patterns that exhibit inherent anisotropy in the angular distribution of critical dimensions. Furthermore, a better simulation accuracy with Manhattanized ILT mask of different MRC levels was obtained with the model calibrated with the all-angle gauges.
Roughness cannot be ignored as feature sizes shrink with Moore's Law, since it has potential to influence the device's performance. The roughness is usually described by line edge roughness (LER) and line width roughness (LWR). LER is the deviation of a feature edge from its ideal shape and is defined as three times the standard deviation, the deviation from the average line width is defined as LWR. For a certain critical dimension (CD) and pitch, there are many factors that can contribute to the roughness in the lithography process, such as source, mask optimizations, photoresist types and its processing, etc. An in-depth insight of the roughness formation mechanisms is essential to improve LER. This study employs photoresist process simulation to analyze LER, offering an efficient alternative to silicon data collection. Simulation analysis is carried out to examine the key factors influencing LER, including quencher concentration, photoacid diffusion length, PEB temperature. Concurrently, the study also delves into the impact of photoresist resin molecular composition and the development process on roughness. By using simulation to understand and predict roughness, the research provides insights into optimizing lithography parameters, thereby improving process stability and minimizing roughness formation.
Inverse lithography technology (ILT) has been the focus of research for several years due to its ability to produce theoretically optimal mask shapes. However, its widespread adoption has been hindered by the complex computational techniques involved and the challenges associated with writing curvilinear ILT mask shapes. To enhance manufacturability, one approach involves streamlining the curvilinear mask shapes by converting them into simplified, ‘Manhattanized’ rectangular shapes using a mask rule constraint (MRC) compliant ILT method. The aim of this study is to examine the influence of mask fracture sizes on manufacturability and to assess the impact of traditional optical proximity correction (OPC), curvilinear ILT, and Manhattanized ILT on the quality of photographic images. The study focuses on challenging cell structures, and generating pattern shapes using traditional OPC, curvilinear ILT, and Manhattanized ILT with MRC compliance. Fracture sizes were varied from 5nm to 25nm in increments of 5nm. To compare mask manufacturability across different patterns, several factors were evaluated, including data fracturing, writing time, and metrology. Photographic image quality metrics, such as NILS (Normalized Image Log-Slope), MEEF (Mask Error Enhancement Factor), EPE (Edge Placement Error), PV-band (Process Variation Band), and CDOF (Common Depth of Focus) were also assessed. The comprehensive analysis aims to provide a better understanding of the trade-offs between different approaches and guide future improvements in mask manufacturability and image quality.
Test pattern selection plays a vital role in the model calibration in the optical proximity correction process. Traditional OPC resist models mainly use the image parameters such as the minimum intensity, the maximum intensity, the slope of intensity along the cut lines crossing the gauge points as their input parameters to calculate the resist contour position. To guarantee the accuracy of the resist model over the whole design layout, it is important that the image parameter space of the test patterns used to calibrate the OPC model covers the image parameter space of the original design layout. We present a method to generate test patterns based on the provided image parameters. The method is based on the adversarial neural network. With this method, we can prepare the test patterns with the desired image parameter coverage.
As chip feature sizes have continued to shrink, resolution enhancement techniques such as Optical Proximity Correction (OPC) have been utilized in advanced technology nodes. In recent years, Inverse Lithography Technology (ILT), a new OPC technique, has been widely applied in advanced Logic and Memory applications to improve imaging performance. Compared to the conventional OPC, ILT enables better process windows (PW) with low edge placement error (EPE) and high wafer critical dimension uniformity (CDU), etc. However, the nonrectilinear mask shapes in ILT make mask writing extremely complex and slow, which can potentially cause more mask manufacturing errors. Therefore, it’s important to quantitatively study the MEEF in ILT masks. In this work, we studied the MEEFs of 2D patterns corrected by ILT and conventional OPC and the differences between these two techniques. The results show that the MEEF at different positions (local MEEF) on an ILT mask has a bigger mean of ~3.14 and a smaller σ of ~0.09 relative to the mean of ~2.14 and σ of ~0.67 from a conventional OPC mask. The MEEF budget is analyzed based on the separated main features (MF) and subresolution assist features (SRAF). With SRAFs being inserted into the entire layout of the ILT mask, it contributes to all individual patterns with ~ 45% (1.49) of the total MEEF. Meanwhile, a conventional OPC mask only has SRAFs on the edges. Thus, SRAFs only contribute MEEF to the patterns located in the edge region (within the proximity effect range). Thus, the main center region of the OPC Mask has a lower MEEF contribution (~1.7). These results suggest that in the ILT recipe tuning process, MEEF should also be included in the cost function as a nonlinear factor so that the inversion can minimize MEEF while optimizing PW and EPE. Furthermore, the manhattanization of the ILT Mask can effectively reduce MEEF.
The technology node shrinks years after years. To guarantee the functionality and yield of IC production, the resolution enhancement technology becomes more and more important. Both optical proximity correction and inverse lithography technique need a precisely calibrated lithographic model. A mask of test patterns needs to be prepared and the lithographic experiment has to be done with it to obtain the CD SEM data for the model fitting. It is beneficial to select the test pattern efficiently. Fewer number of test patterns should be selected without compromising their coverage capability and the accuracy of the lithographic model. We present a machine learning method based on the convolutional autoencoder and core set selection method to achieve above goal. We optimize the existing test pattern mask by selecting parts of gauges out. The OPC models calibrated with the selected data are compared with the models calibrated with original test patterns to evaluate our method.
Mask corner rounding refers to the unintentional rounding deviation of sharp corners or edges during the mask making process, that is caused by the inherent limitations of the e-beam exposure system, such as beam blur, proximity effects, and the resist exposure process. It can have significant consequences on the lithography of chip manufacturing. This article compares the mask corner rounding behavior under different electron beam sizes and presents a novel Optical Proximity Correction (OPC) approach that incorporates mask corner rounding for various dimensional rectangular shapes, named Rounded Corner Aware OPC (RC-OPC). Contrasting with traditional OPC that rely on a single value for simulating mask corner rounding, this innovative OPC approach delivers substantial advantages including increased accuracy, exceptional lithographic performance, and better pattern fidelity, leading to a more dependable and robust process.
The contour data extracted from SEM wafer images after the lithography are widely used in the critical dimension (CD), edge placement error (EPE) measurement. It is important to obtain the contours fast and accurate before the analysis of lithographic process and calibration of the lithographic models. Without the accurate contour data, the complete CDU, PVband analysis and inverse lithography technique are hard to realize. With the continuous shrink of the technology nodes, the demand for the accurate contour extraction increases. However, fast and accurate contour extraction from SEM images with defects and noises is challenging. We apply the U-Net to the semantic segmentation of SEM images. The contour extraction and evaluation can be done better after the image segmentation. Our experimental results show that satisfactory contour data of various types of lithographic patterns can be obtained with noisy SEM images.
OPC is a key step to improve design fidelity when people transfer patterns from the photomask to the wafer. However, to complete a traditional OPC job in advanced technology node, a huge number of CPU cores and above several days are required. In this article, we proposed a pixel based OPC and deep learning OPC hybrid optimization framework. First, the pixOPC is done with the raw training clips. The pairs of the raw training clip and post OPC clip form the training data set. The training clip pairs are fed into GAN (Generative Adversarial Network) OPC architecture and the GAN network is trained. The GAN OPC generator is then validated to ensure that it has enough accuracy and does not overfit the data. The validated GAN OPC generator is then applied to generate OPC masks for the new design clips and the generated masks are refined with traditional OPC to exclude some unexpected outliers generated by the GAN method. We design the reversed high discretion pix2pix GAN to generate OPC masks. Its runtime and performance are compared with the model based OPC, pixOPC and U-Net. The generated OPC masks, simulated lithographic contours, EPE, PVBAND and NILS are compared. We find the GAN generative models have better performance compared with the traditional OPC, and the runtime are also much shorter.
As increasing complexity of1 devices and scaling have continued to push the lithography to low k1 limit, lithographic scientists have been developing various resolution enhancement techniques (RET) to extend 193nm immersion lithography. Chrome-less phase shift mask (PSM) is one of the RET techniques which can produce frequency doubling to half the pitch. The shifter is changed from MoSi to quartz for chrome-less PSM. And the shifter in quartz that is challenging to control at mask etch process. This will cause phase error, lead to image shift and CD asymmetry impacts wafer CD uniformity (CDU) due to intensity imbalance. In this paper, based on aerial image simulations, the conditions to generate frequency doubling have been studied, the resolution limit of the frequency doubling has been investigated. The phase error tolerance of frequency doubling for accepted wafer CDU referring ITRS road map plus budget breakdown to reticle CDU contribution has been studied. The phase error tolerance for smaller pitch is predicted with polynomial fitting extend too.
Mask tape-out is a frequent job in wafer fabrication factories and research institutes. Frame generation is one of the important steps in mask tape-out flow. It requires extensive lithography, process integration, and mask tape-out experience; a large amount of manual work and various data preparation is included, especially when multiple products are combined into a single mask and all product conditions need to be fulfilled simultaneously. When more factors need to be considered, mistakes can be made. We develop a methodology to help frame generation, such as alignment and overlay mark design, selection and placement. It has demonstrated the ability to guide people in error-proofing work, support for frame GDS automatic generation and metrology recipe automatic generation. This is a user-friendly methodology that can reduce the frame generation difficulty and generation time from several weeks to a few minutes.
Inverse lithography technology (ILT) can optimize the mask to gain the best process window and image quality when the design dimension shrinks. However, as a pixel level correction method, ILT is very time-consuming. In order to make the ILT method useful in real mask fabrication, the runtime of ILT-based optical proximity correction mask must evidently decrease while keeping the good lithographic metric performance. Our study proposes a framework to obtain the curvilinear ILT mask with generative adversarial network (GAN). It is subsequently refined with the traditional ILT to exclude unexpected outliers generated by the GAN method. We design conditional GAN, reverse GAN (RGAN), and high discretion GAN (HDGAN) to generate curvilinear ILT mask. Their runtime and the performance are compared. Compared with the CILT method, the speed of GAN type methods with the afterward refinement is increased by an order of magnitude. The RGAN has a better performance in edge placement error and process variation band evaluation, and HDGAN has a better performance in the mask error enhancement factor evaluation. The designed RGAN and HDGAN are promising in actual application to generate the curvilinear mask. They can evidently decrease the runtime and have better lithographic metric performance.
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