A chip-scale PIC packaging approach is presented for high-frequency devices. The PIC is attached with a multilayer ceramic interposer and the active devices are hermetically sealed in between the PIC and the interposer. The ceramic interposer part provides high-bandwidth RF lines and integration of the electronic ICs and passives, whereas the active photonic chips can be mounted on the PIC and a fiber array attached for the optical interface. The co-packaging approach was optimized and demonstrated for 3-µm SOI PIC platform integrated with low-temperature co-fired ceramics (LTCC) interposers.
Development of InP-based U-bend waveguide gain chips for hybrid integration on silicon platform is presented. We utilize Euler bend geometry to ensure small footprint along with low losses. The geometry allows to bring the input and output on the same facet and is used to simplify alignment for lower coupling losses. The interface between bend and straight waveguide is inspected by comparing shallow and deep etched waveguide profiles. The effects of this interface and the bend geometry on the device losses, electric properties and spectrum are reported. Finally, the integration of U-bend gain chips on silicon-on-insulator platform is demonstrated.
An example of continue breakthrough in Silicon Photonics (SiPh) is heterogeneous integration of active devices at wafer level not just to overcome the natural band-gap limit of the Silicon, but more importantly to exploit its high level of integration, significantly reducing packaging costs while driving down the cost of optical communications. In this paper, we describe a powerful combination and coupling of integrated 45°up-reflecting mirrors with longwavelength InP vertical cavity surface emitting lasers (VCSELs) used to develop a TX module with aggregated capacity up to 2-Tb/s capacity. The Photonic Integrated Circuit (PIC) designed and developed under the H2020 research project PASSION, heterogeneously embeds 40 VCSELs covering the C band on a single 3μm -thick Silicon-On-Insulator (SOI) multiplexer chip. The PIC exit-waveguide is also terminated with an up-reflective mirror and coupled with a fiber optic– based periscope, minimizing the form-factor while improving mechanical reliability of the overall packaged module. VCSELs are directly modulated with Discrete Multi-Tone (DMT) modulation format allowing 50 Gb/s rate per VCSEL. The PIC dimension is about 20 x 20 sqmm and power consumption < 5 pJ/bit at 2Tb/s. A Land Grid Array (LGA) interposer hosting the PIC sorrounded by 40 (flip-chip bonded) linear VCSEL drivers, providing electrical and thermal decoupling to the PIC is also described, achieving a compact and a thermally efficient packaging solution. Conveniently, a modular approach is pursued using the same identical 2-Tb/s TX module when building up a supermodule enabling an aggregating capacity up to 16 Tb/s on a single polarization state.
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