This paper presents a study on a new method to create exposure profiles that are optimized for selected die areas where patterning is critical. This new “region of interest leveling (L-ROI)” method caters for trends in the memory market, where intra-die topography with height steps between for instance cell and periphery areas is commonly observed for several 3D-NAND and DRAM device layers. The method takes advantage of the presence of (periphery) die areas where for some device layers patterning is less important than for other, more critical die areas, like the cell area in 3D-NAND. The L-ROI exposure profiles are insensitive to intra-die topography and to variation of the intra-die topography. They result in tighter focus uniformity (FU) in regions of interest, and thus in tighter CDU as well, than conventional exposures at the cost of an accepted performance degradation in other, non-care areas. Results of a study on a VNAND channel hole layer are presented, including focus performance simulation results and CDU measurement results from in-resist verification of L-ROI functionality on an immersion lithography scanner. The latter show a 31.7% CDU improvement with respect to conventional exposure mode.
Process window qualification using focus-exposure wafers is an essential step in lithography and a key use case for CD-SEM metrology. An automated analysis using the correlation between CD and focus/dose is easily possible but rarely done due to missing safety checks. Pattern fidelity that is analyzed by eye and problematic focus/dose conditions that may cause pattern degradation are excluded by hand. Specifically, when EUV lithography is utilized for exposing the most critical layers, roughness estimation becomes much more important, as it will restrict the process window further. We develop and describe unbiased and stable roughness estimates for contact hole patterns and integrate them into the process window analysis pipeline and inline monitoring routine. The analysis goes beyond simple roughness values and can detect a variety of possible CD-SEM measurement problems and shape deviations as well. Furthermore, we introduce a novel image-based machine-learning approach to detect outliers and quantify defective or abnormal patterns. Notably, the underlying model does not require knowledge of the types of CD features or design information for which outliers should be detected. We demonstrate that the approach can reliably detect local defects and a variety of other pattern anomalies. Using the generated visualizations, images with anomalous features can be flagged automatically and the locations of the defects or deviations are pinpointed. The approach yields not only the final missing piece in automated process window qualification, but also new opportunities to monitor pattern fidelity in lithographical semi-conductor processes.
An absolute alignment measurement of an underlayer and overlayer of overlay mark enables an innovative overlay control by which each layer’s grid errors can be independently corrected, versus of a conventional relative overlay measurement and control. We demonstrate an absolute alignment measurement of stacked overlay marks such as Diffraction-Based Overlay (DBO) by adopting a unique method incorporated in a standalone, image-based alignment metrology system. An alignment accuracy of each layer is evaluated using product wafers by comparing alignment measurement result to the reference data. In conclusion, we were able to achieve R2>0.97 coefficient.
Local CD uniformity (LCDU) is being considered as one of key parameter indicators of patterning quality control due to continuous pattern shrinkage and maintaining wafer quality in lithography process. In optical DUV lithography, LCDU has various contributors and they are systematic mask/OPC items, SEM metrology reproducibility, and stochastic effects. In stochastic term, it includes photoresist and speckle contrast. In general, photoresist is considered as the dominant factor in LCDU control, but speckle contrast is drawing attention due to importance of controlling LCDU in new device. Speckle is a light interference effect which causes the non-uniform dose delivery to mask and wafer, and we experimentally confirmed the effect of speckle contrast in several layers. In this paper, we will propose estimated the speckle budget of total LCDU in the target layers through the experiment.
EUV lithography is a technology enabling next generation electronic devices, but issues with photoresist sensitivity,
resolution and line edge roughness as well as tool downtime and throughput remain. As part of the industry's efforts to
address these problems we have worked with resist suppliers to quantify the relative contamination rate of a variety of
resists on EUV multilayer mirror analogues following ASML approved protocols. Here we present results of our
ongoing program to better understand the effect of process parameters such as dose and resist thickness on the
contamination rate of ruthenium coated witness plates, additionally we present results from a study on the effectiveness
of hydrogen cleaning.
During exposure in an EUV scanner, photoresist and other materials coated on a wafer are known to outgas various species. As a requirement to pattern materials in an ASML NXE scanner, these materials need to be screened for outgassing and possible optics contamination. As part of the testing process, a resist-coated wafer is exposed in a vacuum chamber mimicking the conditions inside an EUV scanner. The resist exposure source can be either EUV photons or electron beam (e-beam). This presentation will cover the results to date on a SEMATECH program to study resist outgassing from both the commercial system from EUV Tech and a custom Resist Outgassing and Exposure (ROX) tool. The EUV Tech results reported will be based on electron exposures of the photoresist, and the ROX results reported will be based on EUV photon exposures of the photoresist. The results reported will cover both tools and the measurements of over 80 commercial photoresists.
Extreme ultraviolet lithography (EUVL) is the leading next-generation lithography (NGL) technology to succeed optical
lithography at the 22 nm node and beyond. EUVL requires a low defect density reflective mask blank, which is
considered to be one of the top two critical technology gaps for commercialization of the technology. At the
SEMATECH Mask Blank Development Center (MBDC), research on defect reduction in EUV mask blanks is being
pursued using the Veeco Nexus deposition tool. The defect performance of this tool is one of the factors limiting the
availability of defect-free EUVL mask blanks. SEMATECH identified the key components in the ion beam deposition
system that is currently impeding the reduction of defect density and the yield of EUV mask blanks. SEMATECH's
current research is focused on in-house tool components to reduce their contributions to mask blank defects.
SEMATECH is also working closely with the supplier to incorporate this learning into a next-generation deposition tool.
This paper will describe requirements for the next-generation tool that are essential to realize low defect density EUV
mask blanks. The goal of our work is to enable model-based predictions of defect performance and defect improvement
for targeted process improvement and component learning to feed into the new deposition tool design. This paper will
also highlight the defect reduction resulting from process improvements and the restrictions inherent in the current tool
geometry and components that are an impediment to meeting HVM quality EUV mask blanks will be outlined.
Image placement (IP) and overlay error specifications are serious concerns for lithography at each
successive technology node. Some of the primary contributors to image placement error (IPE) in EUV
lithography are reticle and chuck surface non-flatness and chucking flatness non- uniformity. Flatness
compensation has been proposed as a method to relax flatness specification for EUV substrates. However,
in order for flatness compensation to work effectively, the various components of IPE i.e., reticle flattening
and as-chucked z-height variation needs to be estimated accurately. Flatness compensation models assume
a completely flat, rigid chuck and conformal clamping of the reticle backside. In this paper we will describe
experiments designed to verify the different assumptions that the flatness compensation models are based
on. The experiments involve printing wafers using a set of reticles of different flatness specifications on the
ASML EUV Alpha Demo Tool (ADT) in Albany, NY. We will discuss results from these experiments and
use Finite Element Modeling to simulate reticle chucking to correlate these results to physical properties
electrostatic chuck on the ADT.
Image placement (IP) and overlay error specifications in the International Technology Roadmap for
Semiconductors (ITRS) continue to get tighter with each successive technology node. One of the
significant contributors to IP error is the non-flatness of the reticle substrate. In this paper, we will discuss
in detail the effect of reticle substrate shape on the overlay performance in extreme ultraviolet (EUV) tools.
Substrate shape-induced overlay effects are important when multiple device levels are printed using EUV
lithography. We present an analysis of 20 blanks with different flatness specifications for overlay
signatures when used for printing multiple device levels. A comprehensive analysis of scanner correctable
and non-correctable errors for different substrate shapes will also be presented. Non-flatness specifications
for EUV blanks will be reviewed based on these reticle-matching results. We will discuss results from
flatness measurements and the effect on overlay budget due to mismatched substrates using several
substrates with different flatness specifications.
In extreme ultraviolet lithography (EUVL), mask non-flatness contributes to overlay errors in EUVL scanners. Tight
non-flatness targets are required to meet future overlay; for example, the International Technology Roadmap for
Semiconductors (ITRS) requires that substrate non-flatness will need to decrease to 36 nm peak-to-valley in 2013. To
meet these tight non-flatness values, suppliers must use aggressive polishing steps, adversely impacting substrate yield
and mask blank cost of ownership. An alternative option is to use image placement corrections at the writing step of the
reticle to compensate for the predicted impact of the non-flatness pattern placement errors, which would allow the
specifications to be relaxed.
In this paper, we will present the results of using e-beam image placement corrections during mask writing to
compensate for mask non-flatness. A low thermal expansion material (LTEM) substrate with about 500 nm of nonflatness
was employed. Three different compensation methods were used to calculate the predicted image placement
errors based upon the mask non-flatness, including the expected errors from scanner chucking. The mask was designed
to use a repeating set of four ASML alignment marks (XPA marks) across the mask. During e-beam writin, one mark
was left uncompensated, and the three different compensation methods were applied to the remaining marks. The masks
were exposed using the ASML alpha demo tool (ADT). An overview of the viability of e-beam correction
methodologies to compensate for mask non-flatness is presented based upon the wafer overlay results.
For successful implementation of extreme ultraviolet lithography (EUVL) technology for late cycle insertion at 32 nm
half-pitch (hp) and full introduction for 22 nm hp high volume production, the mask development infrastructure must be
in place by 2010. The central element of the mask infrastructure is contamination-free reticle handling and protection.
Today, the industry has already developed and balloted an EUV pod standard for shipping, transporting, transferring,
and storing EUV masks. We have previously demonstrated that the EUV pod reticle handling method represents the best
approach in meeting EUVL high volume production requirements, based on then state-of-the-art inspection capability at
~53nm polystyrene latex (PSL) equivalent sensitivity. In this paper, we will present our latest data to show defect-free
reticle handling is achievable down to 40 nm particle sizes, using the same EUV pod carriers as in the previous study
and the recently established world's most advanced defect inspection capability of ~40 nm SiO2 equivalent sensitivity.
The EUV pod is a worthy solution to meet EUVL pilot line and pre-production exposure tool development requirements.
We will also discuss the technical challenges facing the industry in refining the EUV pod solution to meet 22 nm hp
EUVL production requirements and beyond.
KEYWORDS: Extreme ultraviolet lithography, Interferometry, Photomasks, Reticles, Data modeling, 3D modeling, Mathematical modeling, Photography, Image quality, Control systems
Extreme Ultraviolet Lithography (EUVL) is one of the leading candidates for Next-Generation Lithography in the sub-45-nm regime. Successful implementation of this technology will depend upon advancements in many areas,
including the quality of the mask system to control image placement errors. For EUVL, the nonflatness of both the
mask and chuck is critical, due to the nontelecentric illumination during exposure. The industry is proposing to use an
electrostatic chuck to support and flatten the mask in the exposure tool. The focus of this research is to investigate the
clamping ability of a pin-type chuck, both experimentally and with the use of numerical simulation tools, i.e., finite
element modeling. A status report on electrostatic chucking is presented, including the results obtained during
repeatability studies and long-term chucking experiments.
Extreme ultraviolet lithography (EUVL) has stringent requirements on image placement (IP) errors in order to allow for
the patterning of devices with critical dimensions (CD) in the sub-32 nm regime. A major contributor to IP error in
EUVL is non-flatness of the mask. Electrostatic chucks are used to support and flatten masks in EUVL scanners.
Proper operation requires that the electrostatic forces generated by the chuck be of sufficient magnitude and be uniform
over the entire chucking area. Hence, there is a need to measure the clamping pressure distribution to properly
characterize performance of electrostatic chucks. This paper discusses two methods to measure electrostatic pressure
magnitude and uniformity by examining the distortion of thin substrates (wafers) during chucking. In the first method, a
wafer with lithographically defined mesas is chucked with the mesas located at the interface between the wafer and the
chuck and thus results in a void near the mesa after chucking. Analytical and finite element models were used to relate
the resulting void radius to the electrostatic pressure and used to assess the feasibility of the technique. Measurements of
pressure on a slab chuck were conducted to demonstrate the mesa measurement approach. The second measurement
method examines the deflection of a wafer between pins on a pin chuck in order to estimate the local pressure. A 3D FE
model was developed to predict the deformation of the wafer between the pins as a function of applied pressure. The
model was used to assess the feasibility of the approach and provide guidance on selecting appropriate substrates for use
in such experiments.
According to the International Technology Roadmap for Semiconductors, meeting the strict requirements on image
placement errors in the sub-45-nm regime may be one of the most difficult challenges for the industry. For Extreme
Ultraviolet Lithography (EUVL), the nonflatness of both the mask and chuck is critical as well, due to the
nontelecentric illumination during exposure. To address this issue, SEMI Standards P37 and P40 have established the
specifications on flatness for the EUVL mask substrate and electrostatic chuck. This study investigates the procedures
for implementing the Standards when measuring and characterizing the shapes of these surfaces. Finite element
simulations are used to demonstrate the difficulties in supporting the mask substrate, while ensuring that the measured
flatness is accurate. Additional modeling is performed to illustrate the most appropriate methods of characterizing the
nonflatness of the electrostatic chuck. The results presented will aid in identifying modifications and clarifications that
are needed in the Standards to facilitate the timely development of EUV lithography.
With the stringent requirements on image placement (IP) errors in the sub-65-nm regime, all sources of mask
distortion during fabrication and usage must be minimized or corrected. For extreme ultraviolet lithography, the
nonflatness of the mask is critical as well, due to the nontelecentric illumination during exposure. This paper outlines
a procedure to predict the IP errors induced on the mask during the fabrication processing, e-beam tool chucking, and
exposure tool chucking. Finite element (FE) models are used to simulate the out-of-plane and in-plane distortions at
each load step. The FE results are compiled to produce a set of Correction Tables that can be implemented during e-beam
writing to compensate for these distortions and significantly increase IP accuracy. A previous version of this paper appeared in the Proceedings of the European Mask and Lithography Conference (EMLC), SPIE, 6533, 653314 (2007). The paper has been updated, retitled, and published here as a result of winning the Best Paper Award at the EMLC.
With the stringent requirements on image placement (IP) errors in the sub-65 nm regime, all sources of mask
distortion during fabrication and usage must be minimized or corrected. For extreme ultraviolet lithography, the
nonflatness of the mask is critical as well, due to the nontelecentric illumination during exposure. This paper outlines
a procedure to predict the IP errors induced on the mask during the fabrication processing, e-beam tool chucking, and
exposure tool chucking. Finite element (FE) models are used to simulate the out-of-plane and in-plane distortions at
each loading step. The FE results are compiled to produce a set of Correction Tables that can be implemented during
e-beam writing to compensate for these distortions and significantly increase IP accuracy.
Characterizing the effect of electrostatic chucking on the flatness of Extreme Ultraviolet Lithography (EUVL) reticles is
necessary for the implementation of EUVL for the sub-32 nm node. In this research, finite element (FE) models have
been developed to predict the flatness of reticles when clamped by a bipolar Coulombic pin chuck. Nonflatness
measurements of the reticle and chuck surfaces were used to create the model geometry. Chucking was then simulated
by applying forces consistent with the pin chuck under consideration. The effect of the nonuniformity of electrostatic
forces due to the presence of gaps between the chuck and reticle backside surfaces was also included. The model
predictions of the final pattern surface shape of the chucked reticle have been verified with chucking experiments and
the results have established the validity of the models. Parametric studies with varying reticle shape, chuck shape, chuck
geometry, and chucking pressure performed using FE modeling techniques are extremely useful in the development of
SEMI standards for EUVL.
Stringent flatness requirements have been imposed for the front and back surfaces of extreme ultraviolet
lithography masks to ensure successful pattern transfer within the image placement error budget. During exposure, an
electrostatic chuck will be used to support and flatten the mask. It is therefore critical that the electrostatic chucking
process and its effect on mask flatness be well-understood. The current research is focused on the characterization of
various aspects of electrostatic chucking through advanced finite element (FE) models and experiments. FE models that
use flatness measurements of the mask and the chuck to predict the final flatness of the pattern surface have been
developed. Pressure was applied between the reticle and chuck to simulate electrostatic clamping. The modeling results
are compared to experimental data obtained using a bipolar Coulombic pin chuck. Electrostatic chucking experiments
were performed in a cleanroom, within a vacuum chamber mounted on a vibration isolation cradle, to minimize the
effects of particles, humidity, and static charges. During these experiments, the chuck was supported on a 3-point
mount; the reticle was placed on the chuck with the backside in contact with the chucking surface and the voltage was
applied. A Zygo interferometer was used to measure the flatness of the reticle before and after chucking. The FE
models and experiments provide insight into the electrostatic chucking process which will expedite the design of
electrostatic chucks and the development of the SEMI standards.
Electrostatic chucks are used to support and flatten extreme ultraviolet lithography (EUVL) masks during exposure
scanning. Characterizing and predicting the capability of electrostatic chucks to reduce mask nonflatness to meet the
required specifications are critical issues. Previous research has assumed that the electrostatic force is uniform over the
entire chucking area; however, recent results from chucking experiments suggest this may not be the case. Quantifying
the spatial nonuniformity in electrostatic force is critical for the understanding and modeling of electrostatic chucking of
masks in EUVL systems. The present research proposes a novel approach to identify the local electrostatic pressure, by
analyzing experimental interferometric data and comparing it to analytical and finite element modeling results. The
local analysis can be expanded to a global prediction spanning the entire electrostatic chucking surface.
Extreme Ultraviolet Lithography (EUVL) is one of the leading candidates for Next-Generation Lithography in the sub-45-nm regime. One of the key components in the development of EUVL is understanding and characterizing the response of the mask when it is electrostatically chucked in the exposure tool. In this study, finite element (FE) models have been developed to simulate the reticle / chuck system under typical exposure conditions. FE simulations are used to illustrate (a) the effects of the nonflatness of the reticle and chuck, (b) the image placement errors induced by back-side particulates, (c) the influence of the coefficient of friction between the reticle and chuck during exposure scanning, and (d) the effects of contact conductance on the thermomechanical response of the reticle. The focus of this paper is to illustrate that mechanical modeling and simulation has now become a fundamental tool in the design of electrostatic pin chucks for the EUVL technology.
Extreme ultraviolet (EUV) masks and mask chucks require extreme flatness in order to meet the performance and timing specified by the International Technology Roadmap for Semiconductors (ITRS). The EUVL Mask and Chucking Standards, SEMI P37 and SEMI P40, specify the nonflatness of the mask frontside and backside, as well as the chucking surface, to be no more than 50 nm peak-to-valley (p-v). Understanding and characterizing the clamping ability of the electrostatic chuck and its effect on the mask flatness is a critical issue. In the present study, chucking experiments were performed using an electrostatic pin chuck and finite element (FE) models were developed to simulate the chucking.
The frontside and backside surface flatness of several EUV substrates were measured using a Zygo large-area interferometer. Flatness data for the electrostatic chuck was also obtained and this data along with the substrate flatness data was used as the input for the FE modeling. Data from one substrate was selected for modeling and testing and is included in this paper. Electrostatic chucking experiments were conducted in a clean-room facility to minimize contamination due to particles. The substrate was chucked using an electrostatic pin chuck and the measured flatness was compared to the predictions obtained from the FE simulation.
Successful implementation of Extreme Ultraviolet Lithography (EUVL) depends on advancements in many areas, including the quality of the mask and chuck system to control image placement (IP) errors. One source of IP error is the height variations of the patterned mask surface (i.e., its nonflatness). The SEMI EUVL mask and chucking standards (SEMI P37 and SEMI P40) describe stringent requirements for the nonflatness of the mask frontside and backside, and the chucking surfaces. Understanding and characterizing the clamping ability of the electrostatic chuck and the effect on the mask flatness is therefore critical in order to meet these requirements. Legendre polynomials have been identified as an effective and efficient means of representing EUVL mask surface shapes. Finite element (FE) models have been developed to utilize the Legendre coefficients (obtained from measured mask and chuck data) as input data to define the surfaces of the mask and the chuck. The FE models are then used to determine the clamping response of the mask and the resulting flatness of the pattern surface. The sum of the mask thickness nonuniformity and the chuck surface shape has a dominant effect on the flatness of the patterned surface after chucking. The focus of the present research is a comprehensive analysis of the flatness and interaction between the nonflat chuck and the mask. Experiments will be conducted using several sample masks chucked by a slab type electrostatic chuck. Results from the study will support and facilitate the timely development of EUVL mask/chuck systems which meet required specifications.
The challenges in fabricating next-generation lithography (NGL) masks are distinct from those encountered in optical technology. The masks for electron proximity lithography, as well as those for ion and electron projection, use freestanding membranes incorporating layers that are different from the traditional chrome-on-glass photomask blanks. As a promising NGL technology, low-energy electron-beam proximity-projection lithography (LEEPL) will be subject to strict error budgets, requiring high pattern placement accuracy. Meeting these stringent conditions will necessitate an optimization of the design parameters involved in the mask fabrication process. Consequently, comprehensive simulations can be used to characterize the sources of the mechanical distortions induced in LEEPL masks during fabrication, pattern transfer, and mounting. For this purpose, finite element (FE) structural models have been developed to identify the response of the LEEPL mask during fabrication and chucking. Membrane prestress, which is used as input in the FE models, was measured on a 200-mm test mask and found to low in magnitude with excellent cross-mask uniformity. The numerical models were also validated both analytically and experimentally considering intrinsic and extrinsic loading of the mask. Finally, simulations were performed to predict the response of the LEEPL mask during electrostatic chucking. FE results indicate that the mask structure is sufficiently stiff to remain relatively flat under gravitational loadings. The results illustrate that mechanical modeling and simulation can facilitate the timely and cost-effective implementation of the LEEPL technology.
Image fidelity is one of the fundamental requirements in lithography and it is becoming more important as feature sizes shrink below 90 nm. Image distortion depends on the mask deformation caused by the intrinsic stress in the film-substrate system. To develop an understanding of stress generation and to control film quality, measuring film stress is essential. In recent years, research laboratories and industry have increasingly adopted indirect methods for determining film stress. All of these methods are based on the measurement of substrate deformation, and the film stress is calculated from the substrate curvature by the local application of Stoney’s equation. When the two principal stresses at each point in the film plane are not equal to each other and their distribution is not uniform, the local application of Stoney’s equation is invalid. Even though the accuracy of the measurement may be high, the stress determined may not be. An alternative technique based on numerical analysis has been developed. The limitations of using Stoney’s equation and the new stress measurement technique are discussed in this paper.
Extending 157-nm lithography to the 70 nm node will be a difficult challenge due to the stringent requirements on image placement accuracy. At the University of Wisconsin Computational Mechanics Center, numerical and experimental studies are being conducted to investigate materials, fabrication processing, and system parameters necessary to achieve the required overlay error budget. This paper provides our latest results for 157-nm reticles, including the photomask / pellicle system. Mask blank fabrication and pattern transfer effects were simulated utilizing three-dimensional finite element (FE) structural models. The pattern-specific in-plane distortions (IPD) induced by each fabrication process step have been determined using the IBM Nighteagle / Falcon layout. To complete the static structural analysis, the effects of bonding a pellicle were also identified. The thermomechanical response of reticles during e-beam patterning and exposure were evaluated utilizing FE heat transfer models. Results from e-beam writing simulations indicate that transient thermal distortions from patterning the Nighteagle / Falcon design are not critical. However, under high throughput conditions, the IPD induced during scanning exposure can become relatively large. The simulation results provide an indication of the total overlay error budget to be expected, and demonstrate the importance of using predictive models to optimize mask system performance in a cost-effective manner.
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