To enable development of novel signal processing circuits, a high-speed surface-channel charge
coupled device (CCD) process has been co-integrated with the Lincoln Laboratory 180-nm RF fully depleted
silicon-on-insulator (FDSOI) CMOS technology. The CCDs support charge transfer clock speeds in excess of
1 GHz while maintaining high charge transfer efficiency (CTE). Both the CCD and CMOS gates are formed
using a single-poly process, with CCD gates isolated by a narrow phase-shift-defined gap. CTE is strongly
dependent on tight control of the gap critical dimension (CD).
In this paper we review the tradeoffs encountered in the co-integration of the CCD and CMOS
technologies. The effect of partial coherence on gap resolution and pattern fidelity is discussed. The impact of
asymmetric bias due to phase error and phase shift mask (PSM) sidewall effects is presented, along with
adopted mitigation strategies. Issues relating to CMOS pattern fidelity and CD control in the double patterning
process are also discussed.
Since some signal processing CCD structures involve two-dimensional transfer paths, many required
geometries present phase compliance and trim engineering challenges. Approaches for implementing non-compliant
geometries, such as T shapes, are described, and the impact of various techniques on electrical
performance is discussed.
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