3-dimensional chiplet device architectures are expected to provide improved device performance, efficiency, and footprint beyond what is capable with 2-dimensional scaling technologies. Thick resist lithography of damascene and plating resists, as well as organic dielectric materials, plays a critical role in chiplet integration. However, thick resist lithography requires viscous resist solutions, specialized tooling, and long processing times. This makes patterning using these resists inherently prone to uniformity issues, which has become a crucial issue for scaling. This work highlights two strategic areas of thick resist patterning development: improved resist coating methods; and enhanced focus control during exposure. Herein, we show a track-based method for carefully controlled uniformity of the resist coating thickness, with some sacrifice of through-put. In addition, we show stepper-based focus methods to account for die level variations in resist and wafer thickness, as well as local topography. Combined, these provide precise cross-wafer control of thick resist dimensions.
This work proposes a methodology to characterize the extent of photoresists’ CD shrink from various SEM landing energy and imaging conditions, using both AFM metrology and post-etch pattern transfer as methods to evaluate the true physical CD. The resist shrink for both 1D and 2D features with varying resist volumes can be quantified through the various metrology techniques and post-etch dimensional data. Once characterized, material response during SEM exposure can be accounted for in any CDSEM data comparison or OPC model.
As development of stacked Nanosheet Gate All-Around (GAA) transistor continues as the candidate technology for future nodes, several key process points remain difficult to characterize effectively. With the GAA device strategy, it is critical to have an inline solution that can provide a readout of physical dimensions that have an impact on the threshold voltage (VT) and yield. Metrology challenges for obtaining these metrics arise from increasingly dense arrays coupled with both high aspect ratios, high numbers of correlated parameters, and increasingly complex 3D geometries. Large area metrology structures can be used for 3D parameters’ process monitoring through techniques such as scatterometry and xray diffraction (XRD) which deliver averaged results over that area, but variation impacting specific devices cannot currently be understood without destructive cross-section. Prior work to characterize the dimensions of these GAA devices has primarily featured optical metrology, X-ray metrology, and critical-dimension scanning electron microscopy (CDSEM), but these techniques have their own challenges at the critical process points. Atomic force microscopy (AFM) had not been utilized due to the aspect ratios and small trench widths which were inaccessible to conventional techniques. However, due to recent advances in scanning and novel probe technologies, AFM is well-suited now to solve these local, three-dimensional challenges. Through this study, we demonstrate AFM characterization of a key process point in the GAA process flow for multiple structures with varying channel lengths, after epitaxial (epi) growth along the Si sidewall. The AFM scan results are compared to CDSEM images for top-down corroboration of topography and to other reference metrology for height correlation. The impact of measured variations in epi height to device performance is also reviewed.
EUV resist characterizations for line and space patterning as a function of dose and illumination conditions for varying pitches down to 28 nm are discussed. The unintentional resist line top loss (LTL) after development has been monitored and analyzed for all experimental conditions. Furthermore, line top roughness (LTR) is introduced, which is a 3 stochastic metric characterizing in-plane roughness related to the top of the resist lines. The main characterization technique employed for this study is atomic force microscopy (AFM) with novel probing algorithms as well as novel tips with diameters down to 5 nm and aspect ratios of 10:1. Additionally, results acquired by critical dimension scanning electron microscopy and optical critical dimension scatterometry are presented. It was found that the unintentional LTL is resist- and pitch-dependent and can be higher than 9 nm at 16 nm half-pitch but does not correlate with line break defect density results. However, LTR measurements of small area scans at dense line/space pitches may be used to draw conclusions about line break defect densities and hence yield. The resist specific metrics, LTR and LTL, allow for fast and early-on evaluation of new chemical formulations and help to forecast pitch- and dose-dependent performance. Furthermore, the results can be used to improve resist model accuracy for optical proximity correction calculations.
KEYWORDS: Critical dimension metrology, Semiconducting wafers, Scanning electron microscopy, Inspection, Electron microscopes, Defect inspection, Data acquisition, Etching, Field effect transistors
In this paper, we tested a novel methodology of measuring critical dimension (CD) uniformity, or CDU, with electron
beam (e-beam) hotspot inspection and measurement systems developed by Hermes Microvision, Inc. (HMI). The
systems were used to take images of two-dimensional (2D) array patterns and measure CDU values in a custom
designated fashion. Because this methodology combined imaging of scanning micro scope (SEM) and CD value
averaging over a large array pattern of optical CD, or OCD, it can measure CDU of 2D arrays with high accuracy, high
repeatability and high throughput.
Scatterometry is emerging as a prominent metrology technique for lithography. Not only does scatterometry produce
line profile information such as sidewall angle and height along with line width, but the speed and nondestructive
nature of scatterometry accommodates in-line process applications. Scatterometry systems employ reflectometry or
ellipsometry to acquire spectra resulting from the interaction of the input radiation and a symmetrical grating array.
The systems may use fixed wavelengths or a range of wavelengths. The output spectral data is dependent on the
material and physical properties of the grating array and surrounding (subsurface, film stack) material layers. Typical
scatterometry draws on mathematically modeled spectra from known optical and physical parameters such as the
grating pitch and the index of refraction and absorption coefficient functions of the film stack materials. The optical
properties of the materials in the film stack are of particular interest and critical to scatterometry. Material vendors
typically supply constants associated with the optical dispersion models of resists and anti-reflective coatings used in
lithography. These constants are most often based on a Cauchy model for optical dispersion, a very simple model.
However, the optical properties of the photoresist or other coatings may not fit well to a Cauchy model or they may
change during process baking, exposure or just from aging. To make an accurate scatterometry model for patterned
photoresist, the material characteristics must also be modeled. Using these parameters, an accurate picture of the
lithographic materials can be generated. These methods can be applied to both dry and immersion lithography.
As immersion lithography gains a foothold in the manufacturing line, many initial processes will use standard dry
photoresist with the application of an immersion topcoat to protect the final lens element of the lithography tool, and
to reduce defects formed from substances leaching out of the photoresist. Although the goal for an immersion topcoat
is to be neutral to the resist process in terms of profiles, process windows, and CD control, many topcoats are not
completely benign. Topcoat induced resist thinning is a common but unwelcome attribute. In this paper we discuss the
use of scatterometry to characterize topcoat induced thickness changes, and use this technique to evaluate several
commercially available products. We will also demonstrate the ability of scatterometry to accurately determine resist
profile changes as a result of focal changes, topcoat interactions, and airborne contamination. Measurement stability
results are also shown, and correlation to CD-SEM and cross-section SEM are provided as a reference metrology.
We present a systematic analysis of the imaging performance for a 0.93 numerical aperture (NA) state-of-the-art immersion lithography scanner and we compare this performance to its dry NA=0.93 counterpart. The increased depth of focus (DOF) enabled by immersion lithography presents a set of advantages for semiconductor manufacturing which we explore in this article. First, we show that 0.93 NA immersion prevents, for a 65nm gate-level process, the need for imposing pitch restrictions with an attenuated-PSM solution; something not possible with an equivalent "dry" process. Second, we demonstrate the superior critical dimension uniformity (CDU) of an immersion process in the presence of realistic focus variations typically encountered in semiconductor manufacturing. Third, we confirm that the through-pitch behavior of "wet" and "dry" scanners is well matched, enabling the possibility of transferring optical proximity corrections (OPC) between the two types of lithography scanners. The transferability of OPC is key to enabling a fast insertion of immersion lithography into the manufacturing process for the 65nm and 45nm nodes. Finally, we conclude that, from an imaging perspective, immersion is ready for high-volume manufacturing.
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