A variety of middle-of-line lithography overlay (OVL) and process window (PW) parameters have been monitored using PDF Solutions Design-for-InspectionTM (DFITM) in 14nm FinFET technology. The DFI system, which incorporates voltage contrast (VC) electron beam (e-beam) technique on PDF Solutions knowledge based test structure designs, has proven to assist lithography overlay control and process diagnostics, covering process loops of epitaxy, metal gate (MG), contact on active (M0A), contact on metal gate (M0P) as well as segmentation cuts of M0A and MG. In-line eBeam scans are performed after Contact CMP, and OVL and PW parameters are extracted from the curve fitting of VC signals responding to misalignment values. For each process module, dedicated test structures with different layout attributes are designed and placed on the wafer to characterize OVL and PW sensitivity to feature density, geometry and substrate doping. In this work, the concept of DFI system, with specific illustration of DFI M0A to MG OVL measurement to assist inline OVL control and process fix is reported. Although eBeam-based Voltage Contrast techniques traditionally have been used to detect Open and Short failures, and cannot be used to directly measure critical dimensions (CD) of patterned features, the DFI system is designed to monitor integrated process window (PW) variation introduced either by an intentional process split or an unintentional process/tool drift in production line. The results presented below demonstrate DFI capability to assist in-line OVL and PW control for yield enhancement, production monitoring, and excursion prevention.
The importance of pattern-based defect study has grown with more complex processes in advanced semiconductor manufacturing. The pattern is the heart of the DPTCO Design Process Technology Co-Optimization approach. But the definition of pattern has been limited by the design rules that can be setup by an individual. Moreover, the huge volume of data points generated by any DRC Design Rule Check type of search forces user to sort and filter out most of them and keep only a manageable count. This effectively reduces the sample space of pattern-based learning. In this work we have employed a new approach of PCYM Pattern Centric Yield Manager where the high count of unique patterns and all its instances in full chip design is retained. It is a fundamental pillar of computational system for semiconductor fabrication where pattern-centric learning can be deployed to study any related process.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.