As critical dimensions shrink to fit advanced process generation requirements, line width roughness (LWR) has become
more and more important.
As design rules for semiconductor devices shrink, the line width roughness approaches the CD of the line itself. This
leads to poor device performance or even device failure. Thus, an accurate process monitor for LWR is required.
CD-SEM measurements for LWR require a reference to verify the accuracy. TEM has traditionally played this role.
However, its destructive nature, the errors induced by sample preparation, the limited data output and long turnaround
time make routine TEM measurement undesirable.
CD-AFM is a non-destructive technique that is able to generate highly accurate three-dimensional profiles of a sample
surface over tens of microns in the X and Y directions with sub-nanometer resolution.
In this paper we present results that show strong correlation between CD-SEM, TEM and inline CD-AFM based on
measurements of an OPC grating. Based on these results, CD-AFM has successfully replaced TEM as the reference
tool of choice for the R&D stage of a 45nm generation process.
To improve this situation, we have successfully adopted in-line X3D AFM to replace FA TEM as the verification tool in
the R&D stage of a 45nm generation process.
Defect inspections performed in R&D may often result in 100k to 1M defect counts on a
single wafer. Such defect data combine systematic and random defects that may be yield
limiting or just nuisance defects. It is difficult to identify systematic defects from defect
wafer map by traditional defect classification where random sample of 50 to 100 defects
are reviewed on review SEM. Missing important systematic defect types by traditional
sampling technique can be very costly in device introduction. Being able to efficiently
sample defects for SEM review is not only challenging, but can result in a Pareto that lacks
in usefulness for R& D and for yield improvement.
To mitigate the issue and to reduce yield improvement cycle in advanced technology, a
novel method has been proposed. Instead of using random sampling method, we have
applied a pattern search engine to correlate defect of interest (DOI) to its pattern
background. Based on the approach we have identified an important defect type, STI cave
defect, to be the major defect type on defect Pareto. For the defect type, stack die map
was generated that indicated a distinctive signature. The result was compared against
design layout to confirm that the defects were occurring at certain locations of design layout.
Afterwards the defect types were reviewed using SEM and in-line FIB for further
confirmation. We have found the cause of this void defect type to be poor gap-fill in
deposition step. Based on the novel technique, we were able to filter out a systematic
defect type quickly and efficiently from wafer map that consist of random and systematic
defects.
Junction leakage control is studied with electron beam (e-beam) defect inspection after tungsten chemical mechanical polishing (WCMP). Leakage-induced bright voltage contrast (BVC) defects are detected. For both wafer to wafer (WtW) and within wafer (WiW), e-beam inspection results strongly correlate with leakage results of wafer acceptance test (WAT). Failure analysis results showed that the junction leakage was caused by lateral diffusion of nickel silicide (NiSi) underneath the spacer. The extrusion length correlates with gray levels of the tungsten plug very well. In this study we found the optimized condition to suppress junction leakage and also confirmed that post WCMP e-beam inspection can be used to monitor and control junction leakage.
Chemical mechanical planarization (CMP) is a challenging process step for manufacturers implementing dualdamascene architectures at the 65 nm technology node. The polishing rate can vary significantly from wafer-to-wafer, across a single wafer, and across a single die, depending on factors including electroplate profile, slurry chemistry, pad wear, and underlying structure. The process is further complicated by the introduction of low-k dielectrics that have significantly different mechanical properties than the harder SiO2 they replace. Picosecond ultrasonics is a nondestructive, small-spot method that can be used for in-line on-product monitoring of metal processes including copper CMP. In this paper we will present gauge-capable picosecond ultrasonic results on copper erosion test structures that also demonstrate excellent correlation with electrical test measurements and TEM results on 65 nm products.
KEYWORDS: Inspection, Scanning electron microscopy, Semiconducting wafers, Transmission electron microscopy, Defect detection, Resistance, Electron microscopes, Tungsten, Failure analysis, Electron beams
Dark voltage contrast (DVC) defects are detected on normally bright tungsten plugs (W-plugs) during the in-line e-beam inspection step. Cross-sectional scanning electron microscope (SEM) and transmission electron microscope (TEM) in a failure analysis (FA) lab verified that DVC defects with different gray level values (GLV) are caused by different resistances of the W-plugs. We found that DVC defects with lower GLV (GLV1) are W-plugs that are open or almost open. DVC defects with higher GLV GLV2 are caused by partially open W-plugs and in-plug voids. Wafer acceptance test (WAT) results correlated well with e-beam inspection results.
KEYWORDS: Atomic force microscopy, Transmission electron microscopy, Scanning electron microscopy, Etching, Nondestructive evaluation, Semiconducting wafers, Silicon, Oxides, Process control, Photodiodes
In the 65nm process development, use traditional top-view SEM and off-line XSEM and TEM to monitor STI profile became insufficient and inefficient. How to find one non-destructive, in-line monitor method to monitor trench depth, step height, and micro-planarity of STI (Shallow Trench Isolation) module profile become more important and
challenge than before. In-line AFM just cover this challenge during 65nm process development stage. In this paper, we report how to use in-line Atomic Force Microscope (AFM) technology to monitor STI module profile. Use of this technology on profile step-height and critical dimension in production facilities offers superior precision,
accuracy, non-destructive. high throughput and cost effective measurement result. Meanwhile, this paper outlines the implementation of AFM based metrology in an automatic production facility. We focus on the process step just after nitride removed, two key applications on this step, one is to monitor the step height difference and the other is to monitor divot depth at the interfaces height difference between the active area and the isolation area within the STI module.
Because the STI step height and divot after oxide fill might dominate the device threshold voltage value(Vt), we check the step height and divot of STI from SiN removed step to the step of thin gate oxide AEI. Then we check and trace where these defect occurred. We also measured 11 points on 300mn wafer to come out one wafer-level topographic chart to monitor its cross-wafer uniformity. Besides, we compared and correlated the AFM measurement result with FA TEM data. It shows good correlation result between X3D AFM and FA TEM. It means this in-line measurement method could efficient act as one important role on advanced STI module process development.
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