Dr. Joe Lee Profile

Dr. Joe Lee

at IBM Thomas J Watson Research Ctr

SPIE Involvement:

Author

Publications (7)

Proceedings Article | 10 April 2024 Presentation

EUV double patterning solution for subtractive metal patterning at 18nm pitch

Christopher Penny, Koichi Motoyama, Hosadurga Shobha, Nabil Azad, Taesun Kim, Shravana Katakam, Johnsoo Kim, Joe Lee, Gideon Oyibo, Jaemyung Choi, Stuart Sieg, Tenko Yamashita, John Arnold, Kisik Choi

Proceedings Volume PC12958, (2024) https://doi.org/10.1117/12.3016092

KEYWORDS: Optical lithography, Extreme ultraviolet, Double patterning technology, Metals, Design and modelling, Ruthenium, Extreme ultraviolet lithography, Copper, Resistors, Resistance

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Proceedings Article | 13 June 2022 Presentation

Patterning options for post-copper metallization on EUV self-aligned double patterning method

Eric Liu, Joe Lee, Nicholas Joy, Yann Mignot, Angelique Raley, John Arnold, Peter Biolsi

Proceedings Volume PC12056, PC1205609 (2022) https://doi.org/10.1117/12.2615458

KEYWORDS: Optical lithography, Metals, Copper, Photomasks, Extreme ultraviolet, Etching, Double patterning technology, Dielectrics, Atomic layer deposition, Transition metals

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For more than two decades and through approximately ten technology nodes, the semiconductor industry has relied upon Dual Damascene copper interconnects. While there is vigorous debate as to the timing and dimensions of the transition, there is a general consensus that there will eventually be a need to replace copper with a different conductor metal. Motivations include copper’s requirement for space-consuming diffusion barriers and the contributions of interfacial electron scattering to higher resistance at smaller dimensions. Researchers such as D. Galla have proposed a range of candidate conductor metals, many of which would be patterned subtractively (by depositing blanket sheets of material and then etching away the portions not required for circuity). There is a growing body of literature considering the choice of metal, methods for controlling its morphology and electrical behavior, and processes for etching it. In this study, we examine a different facet of the transition from Damascene to subtractive conductor formation, specifically the role played by sidewall spacers in pattern formation and transfer. Because the dimensions at which non-Cu conductors may become competitive are well beyond the resolution limits of single exposure EUV, it is likely that an SADP process will be used. The common approach to pattern assembly for Damascene applications is to place mandrels where Cu conductors are ultimately desired, use ALD spacers on the mandrel sidewalls to define minimum-width dielectric spaces, then add a block pattern to define larger regions of dielectric and the remaining “non-mandrel” or “anti-mandrel” conductors. Then the mandrels are removed and the openings in the spacer+block mask are transferred into the dielectric, forming the trenches which will ultimately be filled with Cu. For subtractive metal patterning, preserving the existing circuit design and mask generating infrastructure favors a different approach: mandrels would still be placed at conductor locations and ALD spacers would still be used to define minimum dielectric spaces, but anti-mandrel conductor locations would be covered by new regions of masking material (rather than openings in the block mask). Then the spacers would be removed and the mandrels and anti-mandrel masks would be used to transfer the pattern into the metal below. This study focuses on comparison of the patterning performance of the two approaches using model structures to minimize the confounding impact of the subsequent etch steps (i.e., etching into ULK or metal). Topics of particular interest include LER, LWR, CDU, pitchwalking, and the effects of local variations in pattern density. Methods to improve patterning performance for both schemes will be discussed.

Proceedings Article | 13 June 2022 Presentation

Etch and patterning development for 2nm node nanosheet devices

Eric Miller, Indira Seshadri, Tsung-Sheng Kang, Dominik Metzler, Joe Lee, Stuart Sieg, Sebastian Engelmann, Jeff Shearer, John Arnold, Nelson Felix

Proceedings Volume PC12056, PC120560A (2022) https://doi.org/10.1117/12.2614316

KEYWORDS: Optical lithography, Etching, Plasma etching, Plasma, Nanotechnology, Extreme ultraviolet, Line width roughness, Ions, Fin field effect transistors, Extreme ultraviolet lithography

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Proceedings Article | 6 April 2020 Presentation + Paper

Strategies for aggressive scaling of EUV multi-patterning to sub-20 nm features

Ashim Dutta, Jennifer Church, Joe Lee, Brendan O’Brien, Luciana Meli, Chi Chun Liu, Saumya Sharma, Karen Petrillo, Cody Murray, Eric Liu, Katie Lutker-Lee, Qiaowei Lou, Chris Cole, Angélique Raley, Akiteru Ko, Subhadeep Kal, Jake Kaminsky, Aelan Mosden, Henan Zhang, Shan Hu, Lior Huli, Naoki Shibata, Dave Hetzer, Chia-Yun (Sharon) Hsieh

Proceedings Volume 11323, 113230V (2020) https://doi.org/10.1117/12.2551727

KEYWORDS: Line edge roughness, Lithography, Etching, Amorphous silicon, Extreme ultraviolet, Oxidation, Extreme ultraviolet lithography, Optical lithography, Scanning electron microscopy, Critical dimension metrology

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SPIE Journal Paper | 31 July 2018

Self-aligned blocking integration demonstration for critical sub-30-nm pitch Mx level patterning with EUV self-aligned double patterning

Angélique Raley, Joe Lee, Jeffrey Smith, Xinghua Sun, Richard Farrell, Jeffrey Shearer, Yongan Xu, Akiteru Ko, Andrew Metz, Peter Biolsi, Anton Devilliers, John Arnold, Nelson Felix

JM3, Vol. 18, Issue 01, 011002, (July 2018) https://doi.org/10.1117/12.10.1117/1.JMM.18.1.011002

KEYWORDS: Etching, Extreme ultraviolet, Line edge roughness, Optical lithography, Line width roughness, Silicon, Double patterning technology, Dielectrics, Metals, System on a chip

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Proceedings Article | 4 April 2018 Paper

Self-aligned blocking integration demonstration for critical sub-30nm pitch Mx level patterning with EUV self-aligned double patterning

Angélique Raley, Joe Lee, Jeffrey Smith, Xinghua Sun, Richard Farrell, Jeffrey Shearer, Yongan Xu, Akiteru Ko, Andrew Metz, Peter Biolsi, Anton Devilliers, John Arnold, Nelson Felix

Proceedings Volume 10589, 105890L (2018) https://doi.org/10.1117/12.2297438

KEYWORDS: Etching, Extreme ultraviolet, Line edge roughness, Image processing, Optical lithography, Dielectrics, Silicon, Metals, Line width roughness, Double patterning technology

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Proceedings Article | 24 March 2017 Presentation + Paper

Single-expose patterning development for EUV lithography

Anuja De Silva, Karen Petrillo, Luciana Meli, Jeffrey Shearer, Genevieve Beique, Lei Sun, Indira Seshadri, Taehwan Oh, Seulgi Han, Nicole Saulnier, Joe Lee, John Arnold, Bassem Hamieh, Nelson Felix, Tsuyoshi Furukawa, Lovejeet Singh, Ramakrishnan Ayothi

Proceedings Volume 10143, 101431G (2017) https://doi.org/10.1117/12.2261216

KEYWORDS: Optical lithography, Extreme ultraviolet lithography, Extreme ultraviolet, Lithography, Materials processing, Photoresist processing, Etching, Metals, Quantum efficiency, Photoresist materials, Interfaces, Silicon

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Showing 5 of 7 publications

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