Mr. Jongsu Lee Profile

Jongsu Lee

at SK Hynix Inc

SPIE Involvement:

Author

Publications (9)

Proceedings Article | 22 March 2016 Paper

Manufacturability of dense hole arrays with directed self-assembly using the CHIPS flow

Arjun Singh, Jaewoo Nam, Jongsu Lee, Boon Teik Chan, Hengpeng Wu, Jian Yin, Yi Cao, Roel Gronheid

Proceedings Volume 9777, 97770P (2016) https://doi.org/10.1117/12.2219261

KEYWORDS: Optical lithography, Plasma etching, Materials processing, Manufacturing, Lithography, Process control, Directed self assembly, Polymer thin films, Polymethylmethacrylate, Photoresist materials, Cadmium, Electron beam lithography, Critical dimension metrology

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Proceedings Article | 8 March 2016 Paper

Spacer multi-patterning control strategy with optical CD metrology on device structures

Jongsu Lee, Byoung-Hoon Lee, Won-Kwang Ma, Sang-Jun Han, Young-Sik Kim, Noh-Jung Kwak, Thomas Theeuwes, Wei Guo, Yi Song, Baukje Wisse, Stefan Kruijswijk, Hugo Cramer, Steven Welch, Alok Verma, Rui Zhang, Yvon Chai, Sharon Hsu, Giacomo Miceli, Kyu-Tae Sun, Jin-Moo Byun

Proceedings Volume 9778, 97782B (2016) https://doi.org/10.1117/12.2219664

KEYWORDS: Etching, Metrology, Process control, Control systems, Critical dimension metrology, Scatterometry, Optical lithography, Image processing, Scatter measurement, Measurement devices, Semiconducting wafers, Inspection

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Proceedings Article | 19 March 2015 Paper

Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

Honggoo Lee, Jongsu Lee, Sang Min Kim, Changhwan Lee, Sangjun Han, Myoungsoo Kim, Wontaik Kwon, Sung-Ki Park, Pradeep Vukkadala, Amartya Awasthi, J. Kim, Sathish Veeraraghavan, DongSub Choi, Kevin Huang, Prasanna Dighe, Cheouljung Lee, Jungho Byeon, Soham Dey, Jaydeep Sinha

Proceedings Volume 9424, 94240M (2015) https://doi.org/10.1117/12.2085862

KEYWORDS: Semiconducting wafers, Overlay metrology, Lithography, Scanners, Distortion, Plasma enhanced chemical vapor deposition, Semiconductors, Process control, Manufacturing, Error analysis

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Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes – which is directly related to stresses induced by wafer processing. In multiple instances it was possible to adjust process parameters such as gas flow rate, machine power, etc., and reduce non-uniform stresses in the wafer. Estimates of process-induced overlay errors were also used to perform feedforward overlay corrections for 3D-NAND production wafers. Results from the studies performed in an advanced semiconductor fabrication line are reported in this paper.

Proceedings Article | 19 March 2015 Paper

Improvement of depth of focus control using wafer geometry

Honggoo Lee, Jongsu Lee, Sangmin Kim, Changhwan Lee, Sangjun Han, Myoungsoo Kim, Wontaik Kwon, Sung-Ki Park, Sathish Veeraraghavan, JH Kim, Amartya Awasthi, Jungho Byeon, Dieter Mueller, Jaydeep Sinha

Proceedings Volume 9424, 942428 (2015) https://doi.org/10.1117/12.2085848

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Metrology, Scanners, Lithography, Chemical mechanical planarization, Optical lithography, Semiconductors, Etching, Neodymium

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Proceedings Article | 1 April 2013 Paper

EUV mask defect analysis from mask to wafer printing

Yoonsuk Hyun, Kangjoon Seo, Kyuyoung Kim, Inhwan Lee, Byounghoon Lee, Sunyoung Koo, Jongsu Lee, Sukkyun Kim, Seomin Kim, Myoungsoo Kim, Hyosang Kang

Proceedings Volume 8679, 86790G (2013) https://doi.org/10.1117/12.2010091

KEYWORDS: Photomasks, Inspection, Semiconducting wafers, Particles, Extreme ultraviolet, Wafer inspection, Scanners, Reticles, Extreme ultraviolet lithography, Defect inspection

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Proceedings Article | 3 April 2012 Paper

A scatterometry-based CD uniformity control solution for Spacer Patterning Technology

Jongsu Lee, Chang Moon Lim, Chan-Ho Ryu, Myoungsoo Kim, Hyosang Kang, Hugo Cramer, Noelle Wright, Birgitt Hepp, Liesbeth van Reijnen, Hans van der Laan, Maryana Marun, Peter ten Berge

Proceedings Volume 8324, 83241V (2012) https://doi.org/10.1117/12.917824

KEYWORDS: Critical dimension metrology, Optical lithography, Double patterning technology, Deposition processes, Scatterometry, Semiconducting wafers, Process control, Etching, Metrology, Control systems

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Proceedings Article | 23 March 2012 Paper

Study on CD variation in the vicinity of the exposure field edge in EUV lithography

Chang-Moon Lim, Seokkyun Kim, Jun-Taek Park, Yoonsuk Hyun, Jong-Su Lee, Sunyoung Koo, Myoungsoo Kim, Hyosang Kang

Proceedings Volume 8322, 83221O (2012) https://doi.org/10.1117/12.916108

KEYWORDS: Critical dimension metrology, Photomasks, Extreme ultraviolet lithography, Extreme ultraviolet, Optical proximity correction, Scanners, Deep ultraviolet, EUV optics, Semiconductors, Reticles

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Proceedings Article | 13 March 2012 Paper

Overlay metrology for low-k1: challenges and solutions

Jens Neumann, Jongsu Lee, Kiho Yang, Byounghoon Lee, Taehyeong Lee, Jeongsu Park, Chang-moon Lim, Donggyu Yim, Sungki Park, Eric Janda, Kaustuve Bhattacharyya, Chan-ho Ryu, Young-Hong Min, Kiki Rhe, Bernd Geh

Proceedings Volume 8326, 832602 (2012) https://doi.org/10.1117/12.916376

KEYWORDS: Overlay metrology, Diffraction, Data modeling, Metrology, Diffraction gratings, Lithography, Semiconducting wafers, Inspection, Printing, Computer simulations

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Proceedings Article | 20 April 2011 Paper

Diffraction-based overlay for spacer patterning and double patterning technology

Byoung Hoon Lee, JeongSu Park, Jongsu Lee, Sarohan Park, ChangMoon Lim, Dong-Gyu Yim, Sungki Park, Chan-Ho Ryu, Stephen Morgan, Maurits van de Schaar, Andreas Fuchs, Kaustuve Bhattacharyya

Proceedings Volume 7971, 79712U (2011) https://doi.org/10.1117/12.870473

KEYWORDS: Overlay metrology, Diffraction gratings, Double patterning technology, Diffraction, Optical lithography, Metrology, Resolution enhancement technologies, Semiconducting wafers, Lithography, Scanning electron microscopy

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Showing 5 of 9 publications

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