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Chemo, and grapho epitaxy of lines and space structures are now routinely inspected at full wafer level to understand the defectivity limits of the materials and their maximum resolution. In the same manner, there is a deeper understanding about the formation of cylinders using grapho-epitaxy processes. Academia has also contributed by developing methods that help reduce the number of masks in advanced nodes by “combining” DSA-compatible groups, thus reducing the total cost of the process.
From the point of view of EDA, new tools are required when a technology is adopted, and most technologies are adopted when they show a clear cost-benefit over alternative techniques. In addition, years of EDA development have led to the creation of very flexible toolkits that permit rapid prototyping and evaluation of new process alternatives. With the development of high-chi materials, and by moving away of the well characterized PS-PMMA systems, as well as novel integrations in the substrates that work in tandem with diblock copolymer systems, it is necessary to assess any new requirements that may or may not need custom tools to support such processes.
Hybrid DSA processes (which contain both chemo and grapho elements), are currently being investigated as possible contenders for sub-5nm process techniques. Because such processes permit the re-distribution of discontinuities in the regular arrays between the substrate and a cut operation, they have the potential to extend the number of applications for DSA.
This paper illustrates the reason as to why some DSA processes can be supported by existing rules and technology, while other processes require the development of highly customized correction tools and models. It also illustrates how developing DSA cannot be done in isolation, and it requires the full collaboration of EDA, Material’s suppliers, Manufacturing equipment, Metrology, and electronic manufacturers.
Process, design rule, and layout co-optimization for DSA based patterning of sub-10nm Finfet devices
This course explains how layout and circuit design interact with lithography choices. We especially focus on multi-patterning technologies such as LELE double patterning and SADP. We will explore role of design in lithography technology development as well as in lithographic process control. We will further discuss design enablement of multi-patterning technologies, especially in context of cell-based digital designs.
EUV lithography and DSA haven been accepted by the industry as most promising candidates for dimensional scaling enablement at N7 technology node and beyond. This tutorial explains how introduction of such lithography technologies going to impact layout and circuit design. Choices of lithography would impact physical design and have a significant impact at system level. This tutorial will focus on transition from 193i multi-patterning technologies to EUV lithography and DSA. Factors that would determine on the enablement of these technologies would be highlighted and possible solutions would be shared.
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