Dr. Jung Kyu Chae Profile

Dr. Jung Kyu Chae

Sr. R&D Engineer at imec

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Publications (2)

Proceedings Article | 20 March 2019 Presentation + Paper

CFET standard-cell design down to 3Track height for node 3nm and below

S. M. Y. Sherazi, J. K. Chae, P. Debacker, L. Matti, D. Verkest, A. Mocuta, R. H. Kim, A. Spessot, A. Dounde, J. Ryckaert

Proceedings Volume 10962, 1096206 (2019) https://doi.org/10.1117/12.2514571

KEYWORDS: Transistors, Metals, Logic, Standards development, Nanowires, Silicon, Field effect transistors, Fin field effect transistors, Semiconducting wafers, Electronic components

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Proceedings Article | 20 March 2018 Presentation + Paper

Track height reduction for standard-cell in below 5nm node: how low can you go?

S.M. Yasser Sherazi, Jung Kyu Chae, P. Debacker, L. Matti, P. Raghavan, V. Gerousis, D. Verkest, A. Mocuta, R.H. Kim, A. Spessot, J. Ryckaert

Proceedings Volume 10588, 1058809 (2018) https://doi.org/10.1117/12.2297191

KEYWORDS: Metals, Dielectrics, Standards development, Optical lithography, Logic, Photomasks, Transistors, Extreme ultraviolet, Silicon

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