Mr. Kaushik Sah Profile

Kaushik Sah

Principal Engineer at KLA Corporation

SPIE Involvement:

Author

Area of Expertise:

Process Control Solutions , Multivariate analysis & Deep Learning , Design of Experiments , Defect Inspection & metrology , PWQ & EM Simulations , New product development

Websites:

Company Website

Publications (22)

Proceedings Article | 10 April 2024 Presentation + Paper

Presentation + Paper

Pushing the boundaries of random logic metal patterning with low-n EUV single exposure

Syamashree Roy, Arame Thiam, Kaushik Sah, Yannick Feurprier, Nobuyuki Fukui, Kathleen Nafus, Kenichi Miyaguchi, Dieter Van den Heuvel, Balakumar Baskaran, Joost Bekaert, Andrew Cross, Mircea Dusa, Victor Blanco Carballo

Proceedings Volume 12953, 129530X (2024) https://doi.org/10.1117/12.3010868

KEYWORDS: Optical lithography, Semiconducting wafers, Logic, Scanning electron microscopy, Lithography, Design, Extreme ultraviolet

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Proceedings Article | 10 April 2024 Poster + Paper

Poster + Paper

Advanced pattern-centric solutions for R&D and HVM applications

Ray Xu, Zhijin Chen, Chenwei Gong, Di Yin, Khurram Zafar, Kaushik Sah

Proceedings Volume 12955, 129553R (2024) https://doi.org/10.1117/12.3015164

KEYWORDS: Line edge roughness, Semiconducting wafers, Design, Defect detection, Scanning electron microscopy, Line width roughness, Critical dimension metrology, Diffractive optical elements, High volume manufacturing, Bridges

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Proceedings Article | 10 April 2024 Poster + Paper

Poster + Paper

Hotspot discovery and variability analysis for advanced EUV processes

Kaushik Sah, Zhijin Chen, Yao Zhang, Liming Zhang, Cao Zhang, Craig Higgins, Anatoly Burov, Guy Parsey, Pradeep Vukkadala, Roel Gronheid, Arpit Jain, Ramakanth Ramini, Ankur Agrawal, Garima Sharma, Andrew Cross, Syamashree Roy, Victor Blanco

Proceedings Volume 12955, 129553H (2024) https://doi.org/10.1117/12.3011178

KEYWORDS: Stochastic processes, Scanning electron microscopy, Design, Semiconducting wafers, Inspection, Metrology, Extreme ultraviolet lithography, Defect inspection

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Proceedings Article | 10 April 2024 Poster + Paper

Poster + Paper

EPE monitoring with enhanced metrology using KLA pattern-centric solutions

Huan Ren, Kaushik Sah, Guojie Cheng, Xu Gao, Weiwei Tang, Gary Zhang, Xin Li, Ningqi Zhu, Zach Franz, Torben Mikael Hansen, Henrik Hartmann Henrichsen, Vikram Tolani, Roel Gronheid

Proceedings Volume 12955, 1295537 (2024) https://doi.org/10.1117/12.3010816

KEYWORDS: Metrology, Resistance, Inspection, Critical dimension metrology, Design, Scanning electron microscopy, Overlay metrology, Semiconducting wafers, Defect detection

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Edge placement error (EPE) has become a critically important metric in semiconductor manufacturing. EPE quantifies the difference between the designed and printed layout of devices, coupling overlay and critical dimension (CD) of different litho layers. EPE consists of global and local components and can manifest itself between different physical layers of a device (e.g., via, metal) or within a single layer (primarily relevant for multi-patterning). This paper will study the simplest case of a single layer using an N10 litho-etch-litho-etch (LELE) metal layer patterning and will mainly cover global EPE. Monitoring and control of EPE will enable the stability of integrated circuit devices in advanced technology nodes. Inline EPE prediction in the process control loop at previous litho and etch steps enables early wafer status diagnosis and process disposition, which will improve process margin and wafer yield. Overlay and CD are essential inputs for EPE monitoring, prediction and control. Direct measurement of EPE on the device provides a reference value for an EPE model with overlay and CD measured on special targets. KLA’s pattern-centric solutions provide unique and accurate functionality in EPE metrology by analyzing SEM images on devices or targets in combination with the chip design. In this paper, we conduct experiments for EPE modeling and perform reference analysis using KLA’s pattern-centric solutions, targeting a higher pass rate of e-test, lower defectivity and targeted SEM inspection. KLA’s pattern-centric solutions are applied to e-beam images and provide die-to-database analysis by extracting measurements. The resultant EPE analysis can provide a higher correlation between electrical test data and targeted hotspot inspection, and can also be used to build the EPE model, for example, using e-overlay or CD targets. Overall, the results of these studies show good agreement with EPE model predictions and measured EPE by KLA’s pattern-centric solutions on device structures.

Proceedings Article | 9 April 2024 Presentation + Paper

Presentation + Paper

Patterning optimization for single mask bit-line-periphery and storage-node-landing-pad DRAM layers using 0.33NA EUV lithography at the resolution limit

Van Tuong Pham, Jeonghoon Lee, Kaushik Sah, Ying-Lin Chen, Seonggil Heo, Soobin Hwang, Kenichi Miyaguchi, Bappaditya Dey, Maria Chistiakova, Peter De Schepper, Philippe Bezard, Sara Paolillo, Danilo De Simone, Hyo Seon Suh, Victor Blanco

Proceedings Volume 12957, 129570V (2024) https://doi.org/10.1117/12.3010934

KEYWORDS: Printing, Extreme ultraviolet, Optical lithography, Etching, Extreme ultraviolet lithography, Design, Cadmium, Source mask optimization, Scanning electron microscopy, Semiconducting wafers

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Proceedings Article | 21 November 2023 Presentation + Paper

Presentation + Paper

Rigorous 3D probabilistic computational lithography and chip-level inspection for EUV stochastic failure detection

Eunju Kim, Wooseok Kim, Jonggwan Lee, Seongjong Kim, Sukyong Lee, Nohong Kwak, Mincheol Kang, Yongchul Jeong, Myungsoo Hwang, Chang-Min Park, Kyoil Koo, Seongtae Jeong, John Biafore, Mark Smith, Trey Graves, Anatoly Burov, Pradeep Vukkadala, Guy Parsey, Cao Zhang, Kunlun Bai, Janez Krek, Craig Higgins, Sergei Bakarian, Kyeongeun Ko, Roel Gronheid, Kaushik Sah, Andrew Cross, Yi Liu, Alessandro Vaglio Pret, Chris Walker, Vikram Tolani, George Hwa, Peter Hu, Chang Song, Alex Arkhipov, Loemba Bouckou, Chi-Ping Liu, Xiaochun Yang, Kana O'Hara, Donghwan Son

Proceedings Volume 12750, 127500C (2023) https://doi.org/10.1117/12.2687373

KEYWORDS: Stochastic processes, Inspection, Extreme ultraviolet, Computational lithography, Printing, Semiconducting wafers, Photoresist materials, Extreme ultraviolet lithography, Statistical analysis, Physical phenomena

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Proceedings Article | 28 April 2023 Paper

Paper

Patterning assessment using 0.33NA EUV single mask for next generation DRAM manufacturing

Jeonghoon Lee, Sandip Halder, Van Tuong Pham, Roberto Fallica, Seonggil Heo, Kaushik Sah, Hyo Seon Suh, Victor Blanco, Werner Gillijns, Andrew Cross, Ethan Maguire, Ana-Maria Armeanu, Vladislav Liubich, Evgeny Malankin, Xima Zhang, Monica Kempsell Sears, Neal Lafferty, Germain Fenger, Chih-I Wei, Ryoung Han Kim

Proceedings Volume 12495, 124950S (2023) https://doi.org/10.1117/12.2660763

KEYWORDS: Optical lithography, Extreme ultraviolet, Optical proximity correction, Design and modelling, SRAF, Semiconducting wafers, Inspection, Source mask optimization, Printing, Electronic design automation

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Proceedings Article | 27 April 2023 Presentation + Paper

Presentation + Paper

Multi-metrology: towards parametric yield predictions beyond EPE

Franz Zach, Srividya Cancheepuram, Kaushik Sah, Roel Gronheid, Fatima Anis

Proceedings Volume 12496, 124960P (2023) https://doi.org/10.1117/12.2658042

KEYWORDS: Etching, Line edge roughness, Semiconducting wafers, Overlay metrology, 3D modeling, Scanning electron microscopy, Logic, Yield improvement, Optical lithography

Read Abstract +

Variability control has been a key enabler for achieving continuing technology shrinks in both logic as well as DRAM. With ever-tightening requirements, simple one-dimensional metrology and control aspects, i.e. separate variability control for CD and overlay, are no longer adequate [1]. To improve on this approach, simultaneous control of more than one parameter has been discussed to minimize the parametric yield impact. One such example is to improve edge placement error (EPE), a metric where overlay and CD metrology are combined [1]. In this work, we will revisit the EPE concept from the perspective of using established methodologies used in yield modeling. Rather than starting with a litho-centric approach, we cast the problem as a parametric yield loss mechanism driven by patterning parameters. In contrast to the widely disseminated EPE budget that originates from a patterning process-centric view, we introduce a modified analysis framework. The development of the approach discussed in this work starts with well-known yield engineering approaches rooted in defectivity modeling/statistics. It then proceeds towards quantifying and thus allowing a statistically sound quantification and thus prioritization of patterning (i.e. litho or post etch) improvements based on their impact on the yield loss Pareto. In doing so, the new formalism sheds light on what aspects of the EPE distribution most prominently affects yield loss. It also reveals that the ratio of potentially failing instances with a die and the max number of fails tolerable before the die fails plays a role in formulating any kind of budget approach. When putting our concepts to the test we discovered that there is yet another significant contributor affecting the acceptable variation range. We find that the “rigid structure approach”, an inherent assumption in any budget breakdown, and feature-to-feature interactions drive a significant reduction of the available processing tolerances. We attribute this mechanism to the 3D aspects of the patterning process and present a model that can handle the interactions. Finally, we discuss our approach to addressing the fact that process variability happens on length scales that cover several orders of magnitude. We developed a physical budget breakdown that attempts to optimize the tradeoff between sample size and the ability to capture variability over this wide range of length scales. We will postpone our discussion on other sampling-related topics. The question of how one obtains all required metrology data on one wafer in a manufacturing environment will be addressed in a future publication.

Proceedings Article | 1 December 2022 Poster + Paper

Poster + Paper

Single mask solution to pattern BLP and SNLP using 0.33NA EUV for next-generation DRAM manufacturing

Kaushik Sah, Andrew Cross, Sayantan Das, Roberto Fallica, Jeonghoon Lee, Ryoung-Han Kim, Sandip Halder, Ethan Maguire, Ana-Maria Armeanu, Monica Sears, Neal Lafferty, Vlad Liubich, Chih-i Wei, Germain Fenger

Proceedings Volume 12292, 122920W (2022) https://doi.org/10.1117/12.2645953

KEYWORDS: Photomasks, Optical proximity correction, Stochastic processes, Extreme ultraviolet, Semiconducting wafers, Wafer-level optics, Source mask optimization, Manufacturing, Inspection, Signal to noise ratio, Defect inspection

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Proceedings Article | 25 May 2022 Presentation + Paper

Presentation + Paper

EUV based multi-patterning schemes for advanced DRAM nodes

Sayantan Das, Kaushik Sah, Roberto Fallica, Zhijin Chen, Sandip Halder, Andrew Cross, Danilo De Simone, Fergo Treska, Philippe Leray, Ryoung Han Kim, Ethan Maguire, Chih-I Wei, Germain Fenger, Neal Lafferty, Jeonghoon Lee

Proceedings Volume 12055, 1205503 (2022) https://doi.org/10.1117/12.2615644

KEYWORDS: Etching, Photomasks, Extreme ultraviolet, Optical lithography, Double patterning technology

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Proceedings Article | 13 October 2021 Presentation + Paper

Presentation + Paper

Deep learning-based defect detection using large FOV SEM for 28 nm pitch BEOL layer patterned with 0.33NA single exposure EUV

Sayantan Das, Kaushik Sah, Ardis Liang, Hemanta Roy, Kha Tran, Binesh Babu, Arjun Hegde, Andrew Cross, Philippe Leray, Sandip Halder

Proceedings Volume 11854, 118540Y (2021) https://doi.org/10.1117/12.2600954

KEYWORDS: Inspection, Defect detection, Semiconducting wafers, Scanning electron microscopy, Extreme ultraviolet lithography, Critical dimension metrology, Etching

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Proceedings Article | 22 February 2021 Presentation + Paper

Presentation + Paper

Defect characterization of 28 nm pitch EUV single patterning structures for iN5 node

Kaushik Sah, Sayantan Das, Andrew Cross, Kay Peng, Kha Tran, Binesh Babu, Ardis Liang, Danilo De Simone, Philippe Leray, Sandip Halder

Proceedings Volume 11611, 1161128 (2021) https://doi.org/10.1117/12.2584760

KEYWORDS: Semiconducting wafers, Extreme ultraviolet, Electron beam lithography, Optical inspection, Inspection, Wafer-level optics, Wafer inspection, Stochastic processes, Optics manufacturing, Lithography

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Proceedings Article | 22 February 2021 Poster + Paper

Poster + Paper

Defect characterization of EUV Self-Aligned Litho-Etch Litho-Etch (SALELE) patterning scheme for advanced nodes

Kaushik Sah, Andrew Cross, Sayantan Das, Victor Blanco, Luka Kljucar, Sandip Halder, Philippe Leray

Proceedings Volume 11611, 116112H (2021) https://doi.org/10.1117/12.2585779

KEYWORDS: Extreme ultraviolet, Optical lithography, Scanning electron microscopy, Stochastic processes, Lithography, Back end of line, Ultraviolet radiation, Photomasks, Optical inspection, Metals

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Proceedings Article | 8 October 2020 Presentation + Paper

Presentation + Paper

High sensitivity repeater detection with broadband plasma optical wafer inspection for mask defect qualification

Andrew Cross, Kaushik Sah, Vidyasagar Anantha, Balarka Gupta, Ramon Ynzunza, Neil Troy, Kenong Wu, Raghav Babulnath, Meghna Rajendran, Dieter Van den Heuvel, Philippe Leray

Proceedings Volume 11517, 115170U (2020) https://doi.org/10.1117/12.2572912

KEYWORDS: Reticles, Inspection, Wafer inspection, Wafer-level optics, Photomasks, Plasma, Semiconducting wafers, Signal to noise ratio, Algorithm development, Optics manufacturing

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Proceedings Article | 23 March 2020 Paper

Paper

Optical defect inspection solution for EUV stochastics detection

Vidyasagar Anantha, Raghav Babulnath, Veikunth Kannan, Garima Sharma, Shubham Kumar, Kaushik Sah, Andrew Cross, Rahul Lakhawat, Hari Pathangi, Peter De Bisschop

Proceedings Volume 11323, 113231J (2020) https://doi.org/10.1117/12.2552452

KEYWORDS: Stochastic processes, Inspection, Extreme ultraviolet, Semiconducting wafers, Modulation, EUV optics, Defect inspection, Wafer-level optics, Defect detection

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Proceedings Article | 20 March 2020 Paper

Paper

Massive metrology for process development and monitoring applications

Kaushik Sah, Sayantan Das, Shifang Li, Christophe Beral, Andrew Cross, Sandip Halder

Proceedings Volume 11325, 1132528 (2020) https://doi.org/10.1117/12.2553092

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Metrology, Modulation, Inspection, Copper, Chemical mechanical planarization, Defect inspection, Extreme ultraviolet lithography, Back end of line

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Proceedings Article | 26 March 2019 Paper

Paper

Process window discovery methodology for extreme ultraviolet (EUV) lithography

Sandip Halder, Dieter Van den Heuvel, Stephane Lariviere, Philippe Leray, Kaushik Sah, Andrew Cross, Antonio Mani

Proceedings Volume 10959, 109591V (2019) https://doi.org/10.1117/12.2515805

KEYWORDS: Stochastic processes, Inspection, Extreme ultraviolet, Modulation, Semiconducting wafers, Extreme ultraviolet lithography, Optical inspection, Critical dimension metrology, Bridges, Lithography

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Proceedings Article | 3 October 2018 Paper

Paper

EUV stochastic defect monitoring with advanced broadband optical wafer inspection and e-beam review systems

Kaushik Sah, Andrew Cross, Martin Plihal, Vidyasagar Anantha, Raghav Babulnath, Derek Fung, Peter De Bisschop, Sandip Halder

Proceedings Volume 10809, 1080909 (2018) https://doi.org/10.1117/12.2501825

KEYWORDS: Stochastic processes, Inspection, Scanning electron microscopy, Optical inspection, Photomasks, Etching, Extreme ultraviolet, Semiconducting wafers, Printing, Critical dimension metrology

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Proceedings Article | 16 October 2017 Paper

Paper

EUV reticle print verification with advanced broadband optical wafer inspection and e-Beam review systems

Ravikumar Sanapala, Andrew Cross, Moshe Preil, Jin Qian, Shishir Suman, Vidyasagar Anantha, Kaushik Sah, Scott Eitapence, Danilo De Simone, Dieter Van den Heuvel, Philippe Foubert

Proceedings Volume 10451, 104510L (2017) https://doi.org/10.1117/12.2281632

KEYWORDS: Semiconducting wafers, Photomasks, Inspection, Wafer-level optics, Extreme ultraviolet, Reticles, Optical inspection, Oxides, Wafer inspection, Signal to noise ratio

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Proceedings Article | 1 May 2017 Paper

Paper

Assessment of light source bandwidth impacts on image contrast enhancement using process window discovery

Paolo Alagna, Greg Rechtsteiner, Will Conley, Andrew Cross, Kaushik Sah, Sandip Halder

Proceedings Volume 10147, 101471X (2017) https://doi.org/10.1117/12.2260314

KEYWORDS: Light sources, Deep ultraviolet, Optical lithography, Image contrast enhancement, Semiconductors, Immersion lithography, Scanners, Inspection, Modulation, Semiconducting wafers

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Proceedings Article | 28 March 2017 Paper

Paper

Connected component analysis of review-SEM images for sub-10nm node process verification

Sandip Halder, Philippe Leray, Kaushik Sah, Andrew Cross, Paolo Parisi

Proceedings Volume 10145, 101451Y (2017) https://doi.org/10.1117/12.2270492

KEYWORDS: Image processing, Image analysis, Scanning electron microscopy, Optical inspection, Extreme ultraviolet, Modulation, Photomasks, Deep ultraviolet, Semiconducting wafers, Defect inspection

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Proceedings Article | 22 March 2016 Paper

Paper

DSA materials contributions to the defectivity performance of 14nm half-pitch LiNe flow at IMEC

Hari Pathangi, Varun Vaid, Boon Teik Chan, Nadia Vandenbroeck, Jin Li, Sung Eun Hong, Yi Cao, Baskaran Durairaj, Guanyang Lin, Mark Somervell, Takahiro Kitano, Ryota Harukawa, Kaushik Sah, Andrew Cross, Hareen Bayana, Lucia D’Urzo, Roel Gronheid

Proceedings Volume 9777, 97770G (2016) https://doi.org/10.1117/12.2219936

KEYWORDS: Directed self assembly, Metrology, Optical lithography, Silicon, Semiconducting wafers, Etching, Bridges, Polymers, Manufacturing, Scanning electron microscopy, Epitaxy, Lithography, Thin film coatings

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Showing 5 of 22 publications

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