E-beam inspection based on voltage-contrast (VC) defect metrology has been widely utilized for failure mode analysis of memory devices. Variation in e-beam image contrast indicates shorts, opens, and void defect inline inspection in the idle of production line. Meanwhile, accurate measurement of threshold voltage and the source–drain current is required to characterize memory cell through multilayers. However, in the subthreshold region of memory cell, VC is weakened due to gate voltage stimulated by electron dose of e-beam scanning. We developed a modulated beam imaging with the SEM vector scan system to enhance VC contrast and defect inspection capability. Reliability of the modulated electron microscopy is validated by comparing with physical probing test result for process variation of Boron doping and annealing conditions in full wafer processing. VC with the modulated electron microscopy is well correlated to the probing test result. Image contrast of the modulated microscopy can differentiate contact via on floating circuit and disconnected floating circuit. We applied the modulated electron microscopy for inline electrical defect detection at the middle of manufacturing line of integrated circuits. The defect distribution map by the modulated electron microscopy was confirmed to reproduce the physical probe test result. By achieving inline electrical characterization before back end of line, yield loss issues can be detected and characterized 2 weeks earlier than conventional method. Moreover, this ability to detect and characterize memory cell issues inline is supposed to contribute to overcome the yield learning cycle bottleneck.
E-beam inspection based on voltage-contrast defect metrology has been widely utilized for failure mode analysis of memory devices. Variation in E-beam image contrast indicates shorts, opens and void defect inline inspection in the idle of production line. Meanwhile, accurate measurement of threshold voltage and the source-drain current is required to characterize memory cell through multi-layers. However, in the subthreshold region of memory cell, voltage contrast (VC) is weakened due to gate voltage stimulated by electron dose of e-beam scanning. We developed a modulated beam imaging with the SEM vector scan system to enhance VC contrast and defect inspection capability. Reliability of the modulated electron microscopy is validated by comparing with physical probing test result for process variation of Boron doping and annealing conditions in full wafer processing. VC with the modulated electron microscopy is well correlated to the probing test result. Image contrast of the modulated microscopy can differentiate contact via on floating circuit and disconnected floating circuit. We applied the modulated electron microscopy for in-line electrical defect detection at the middle of manufacturing line of integrated circuits. The defect distribution map by the modulated electron microscopy was confirmed to reproduce the physical probe test result. By achieving in-line electrical characterization before back end of line, yield loss issues can be detected and characterized two weeks earlier than conventional method. Moreover, this ability to detect and characterize memory cell issues inline is supposed to contribute to overcome the yield learning cycle bottleneck.
To fix the root cause of electrical failure chips, we do failure analysis by an electrical test. However, this analysis takes much long time because an electrical test is done after a few months since the defect occurred in in-line processes. To reduce the analysis time, we used the defects detected by in-line optical inspections of post semiconductor process steps. In order to identify the position of the defects that caused the failure, we used to match CAD contour with a DR-SEM (Defect Review-SEM) image contour of the defect. But the “hit rate” of the defect was not so high. Here hit rate is a rate that the defects cause an electrical failure chip. There were two reasons. First, the matching success rate was low because extracting contour from SEM is inaccurate. Second, CAD was a mask pattern and didn’t include the circuit node information, so there was an over-detection such as a short between dummy nodes. We propose a high precision in-line schematic failure analysis technique by machine learning and circuit node information. For matching pixel to pixel, we match Fake-SEM generated by GAN instead of CAD with DR-SEM. Next we make the CAD that is added the defect, and a design verification technique LVS generates circuit diagram. When the defect’s diagram is different from reference, we classify the defect cause an electrical failure. We confirmed that this technique could dramatically improve classification accuracy of the defect of root cause in manufacturing with our memory device.
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