Mach-Zehnder Interferometer (MZI) topological cascade architectures, which allow linear transformations between multiple channels simultaneously, are gradually becoming a powerful tool for photonics and have a place in optical neural networks. This paper focuses on the theoretical analysis and software simulation of two unitary matrix architectures for a 6×6 MZI-based optical processor: the triangular architecture and the rectangular architecture. Both unitary arrays are composed of fifteen reconfigurable MZI units, each of which is comprised of two adjustable phase shifters and two 3-dB directional couplers. For a given neural network training application, the value of each phase shifter can be calculated from the matrix factorization process. The theoretical derivation is verified through simulations using the advanced software Max-Optics. When compared with Lumerical INTERCONNECT, the maximum error is less than 0.00044%, and the simulation time is reduced by 3 times.
As the complexity of optoelectronic integrated circuits (OEICs) develop, the need for an accurate and efficient compatible simulation environment that supports both photonics and electronics becomes increasingly critical. This paper addresses the demand by proposing an approach that leverages Verilog-A language to build equivalent circuit models and compact models for photonic devices. Passive components, including couplers and waveguides, are modeled using compact models. Active components, such as CW lasers, are realized through the adoption of equivalent circuit models. Additionally, a depletion-type phase shifter is separated in two parts: the electrical part for parasitic parameters and the p-n junction are presented with RC components, while the optical characteristics, influenced by electrical modulation, are achieved through the use of compact models. The proposed compatible system design scheme, which consists of Verilog-A models, can be analyzed in the frequency-domain using EDA software. The simulation results demonstrate a mean absolute percentage error (MAPE) of less than 0.003% when compared to those obtained from commercial interoperable design software. Therefore, this study effectively addresses the challenge of incompatible design and simulation for OEIC, and providing strong evidence that OEIC design can be achieved in a unified EDA platform.
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