In the realm of Design for Manufacturability (DFM) optimization, Pattern-Based Layout Optimization (PBLO) has been a go-to approach for detecting and repairing DFM violations. However, to enhance the effectiveness of DFM rules in addressing hotspots, it becomes imperative to encompass a broader array of design situations (layout contexts). This expansion leads to an increased number of potential fixing guidance “hints”. Nonetheless, employing a static fixing hint order, unaware to the specific in-design topologies, can potentially diminish the output metrics i.e., fixing rate and runtime performance. In pursuit of optimizing these output metrics, we present an ML-powered PBLO workflow. In this innovative approach, a Machine Learning (ML) model is trained using an extensive dataset of preranked fixing guidance hints that are associated with a DFM rule. The topology aware supervised ML model is trained to dynamically guide and select the most suitable in-design fixing guidance order per situation, ultimately leading to an improved fixing rate, runtime and quality of results. In this study, we illustrate a workflow and mechanism for seamlessly integrating machine learning capabilities into the in-design fixing router. This involves developing multiclass machine learning algorithms and models to facilitate the generation of an optimal fixing guidance sequence.
A pattern replacement in-design auto-fixing methodology, called MAS-POP, is developed to increase the scores calculated by the Manufacturability Analysis and Scoring (MAS) tool, improving the compliance with DFM rules. A library of patterns is developed using pattern classification automation, converting multiple types of Back-End-Of-Line (BEOL) DFM rules to patterns: via-metal line end enclosure, metal 2 tip-to-tip spacing, and metal area. Corresponding fixing hints are prescribed for each pattern. Once the library of patterns and the associated fixing hints have been developed, they are integrated with the router to utilize its pattern replacement feature. This insertion identifies matching patterns and fixes the violations by applying the prescribed fixing hints, improving the usage of the DFM rules and enhancing the MAS scores. The MAS-POP methodology is demonstrated on routed designs. Results show that for a 200 x 200 um2 block, three via-metal line end enclosure patterns reduce the number of DFM violations from 12.5k to 360 on one 2x metal layer, with a small runtime impact.
This paper proposes a new methodology that can greatly accelerate Manufacturability Analysis & Scoring (MAS) deck runtime. The intention of this work is to provide a quick preview check to ensure that a new design will pass MAS signoff. Instead of running the deck on the full design, the input design is sampled down to a few random locations which are then analyzed. Furthermore, the actual MAS checks are replaced by an ML trained lookup methodology that keys off very simple design parameter like layer area density and layer perimeter density. The output of the deck is a simple PASS/FAIL statement and a range forecast for the MAS score based on a statistical assessment. We can demonstrate 4x runtime improvement while incurring minor tradeoffs for accuracy.
KEYWORDS: Data modeling, Machine learning, Neural networks, Design and modelling, Design for manufacturing, Principal component analysis, Correlation coefficients, Singular value decomposition, Mathematical optimization, Lithography
Design for Manufacturability (DFM) physical verification checks using supervised Machine Learning (ML) are developed and optimized to identify via-metal enclosure weak points to prevent via opens caused by line-end shortening post-retargeting. Various methods for generating feature vectors and neural network architectures are evaluated for optimizing training time and ML model quality. Techniques include applying PCA to image-based density vectors generated from layout clips to identify the principle components or using localized layout features directly for model training. Results show that for a sample size of 300k vias, the image-based density vectors versus localized layout feature vectors achieve similar correlation coefficients of 0.95 and normalized RMSE of 0.11, with a training time of 10+ hours versus 1+ minute, respectively.
Design for Manufacturability (DFM) in-design fixing methodologies are developed to improve Manufacturability Aware Scoring (MAS). Two methodologies have been evaluated. For the first methodology, DFM recommended rules are inserted in the reference flow for rip-up-and-reroute, thus fixing DFM rule violations, improving the MAS score. For the second methodology, pattern classification is used to classify the recommended rules into patterns based on the profiling of multiple layout designs. A library of fixable patterns with corresponding fixes is built. The pattern library is then inserted in the rip-up-and-reroute flow to fix the DFM rule violations, improving the MAS score. The methodologies are demonstrated on 28nm technology. Results show an average fix rate of 89.1 % for a design with a core utilization of 0.6 and 78.4% with a core utilization of 0.6 for three DFM MAS enclosure rules, VIA2, VIA3 and VIA4 layers.
Retargeting-aware Design for Manufacturability (DFM) via-metal enclosure checks are developed using supervised machine learning to identify critical weak points to aid layout fixing. The machine learning model is developed using a neutral network architecture. Seventeen localized layout features were extracted, including: side and line end via-metal enclosure, via spacing to the neighboring features, and metal coloring. The extracted features were used to form feature vectors to train and generate a machine learning-based model for predicting post-retargeting, via-metal enclosures. This method was demonstrated on 22nm layouts. Using a neural network with 2-hidden layers, the predicted via-metal enclosure versus the actual data correlate with an R2 of 0.91 and an RMSE 0.0067.
KEYWORDS: Analog electronics, Design for manufacturing, Metals, Resistance, Capacitance, Databases, Back end of line, Tolerancing, Mirrors, Manufacturing
Electrical Design-for-Manufacturability (DFM) checks are developed to quantify layout enhancements and their impact on circuit performance for analog designs. A database containing circuit topologies of analog matched devices is built. Then, connectivity checks scan the schematics for topologies from the database. If a matching topology were detected, the matched devices are mapped to layout for layout matching checks. If layout mismatches are detected, electrical DFM checks are used to quantify the imbalance in terms of parasitic resistance and capacitance. The electrical DFM checks are applied to quantify the impact due to routing, fill, and DFM fixing on three, 22nm analog design blocks. Fill insertion’s contribution to RC change is the greatest followed by routing and DFM fixing, with a maximum change of 7%, 5%, and less than 1%, respectively. Symmetry-aware layout insertions preserve the matching of electrical parameters, showing zero mismatch. All designs pass electrical DFM checks as results are within the expected design tolerances.
A symmetry-aware DFM layout insertion flow for matched circuits is developed for enhancing analog and mixed-signal designs. Pattern capture is used to categorize the matched circuits to unique groups of layout patterns and store them in a pattern database, in which each pattern has an associated group identification, a match location, a region of extent, and a symmetry constraint. Using the stored information in the pattern database, DFM layout insertions are applied to the base pattern and replicated for the symmetric patterns to generate an optimized layout, thus preserving the original symmetry. The impact of the DFM insertions on analog circuit performance was quantified using electronic simulators. The application of symmetry-aware DFM enhancements to analog designs achieves nearly 100% DFM compliance with negligible 0.1-0.2% impact to analog electrical parameters.
KEYWORDS: Design for manufacturing, Analog electronics, Manufacturing, Chemical mechanical planarization, Design for manufacturability, Metals, Extremely high frequency, Yield improvement, Digital electronics, Transceivers
A suite of DFM enablement is enhanced to address the unique needs of analog, RF, and mmWave designs in the custom design flow. The DFM rules and patterns are made stricter beyond baseline requirements, and new DFM rules and patterns are added to further reduce layout-dependent device variability. Auto-fixing in the custom design flow is enhanced to meet these new requirements. New DFM enablement is developed for device matching for differential circuits and sensitive devices. Lastly, novel DFM fill strategies are implemented to reduce the variability of passive devices operating at high frequencies. Using DFM-aware fill, a 2% quality-factor loss for a mmWave inductor operating at 30 GHz is shown to be sufficient for meeting manufacturing planarity requirements.
A pattern matching and rule-based polygon clustering methodology with DFM scoring is proposed to detect decomposition-induced manufacturability detractors and fix the layout designs prior to manufacturing. A pattern matcher scans the layout for pre-characterized patterns from a library. If a pattern were detected, rule-based clustering identifies the neighboring polygons that interact with those captured by the pattern. Then, DFM scores are computed for the possible layout fixes: the fix with the best score is applied. The proposed methodology was applied to two 20nm products with a chip area of 11 mm2 on the metal 2 layer. All the hotspots were resolved. The number of DFM spacing violations decreased by 7-15%.
A pattern-based methodology for optimizing SADP-compliant layout designs is developed based on identifying cut
mask patterns and replacing them with pre-characterized fixing solutions. A pattern-based library of difficult-tomanufacture
cut patterns with pre-characterized fixing solutions is built. A pattern-based engine searches for matching
patterns in the decomposed layouts. When a match is found, the engine opportunistically replaces the detected pattern
with a pre-characterized fixing solution. The methodology was demonstrated on a 7nm routed metal2 block. A small
library of 30 cut patterns increased the number of more manufacturable cuts by 38% and metal-via enclosure by 13%
with a small parasitic capacitance impact of 0.3%.
A pattern-based methodology for optimizing Self-Aligned Double Patterning (SADP)-compliant layout designs is developed based on detecting cut-induced hotspot patterns and replacing them with pre-characterized fixing solutions. A pattern library with predetermined fixing solutions is built. A pattern-based engine searches for matching patterns in the layout designs. When a match is found, the engine opportunistically replaces the detected pattern with a pre-characterized fixing solution, preserving only the design rule check-clean replacements. The methodology is demonstrated on a 10nm routed block. A small library of fourteen patterns reduced the number of cut-induced design rule check violations by 100% and lithography hotspots by 23%.
A pattern-based methodology for optimizing stitches is developed based on identifying stitch topologies and replacing them with pre-characterized fixing solutions in decomposed layouts. A topology-based library of stitches with predetermined fixing solutions is built. A pattern-based engine searches for matching topologies in the decomposed layouts. When a match is found, the engine opportunistically replaces the predetermined fixing solution: only a design rule check error-free replacement is preserved. The methodology is demonstrated on a 20nm layout design that contains over 67 million, first metal layer stitches. Results show that a small library containing 3 stitch topologies improves the stitch area regularity by 4x.
Decomposition-aware layout design improvements for 8, 9, 11, and 13-track 20/14nm standard cells are presented. Using a decomposition-aware scoring methodology that quantifies the manufacturability of layouts, the Double Patterning Technology (DPT)-compliant layouts are optimized for DPT-specific metrics that include: the density difference between the two decomposition mask layers, the enclosure of stitching areas, the density of stitches, and the design regularity of stitching areas. For a 9-track standard cell, eliminating the stitches from the layout design improved the composite score from 0.53 to 0.70.
A pattern matching methodology that identifies non-decomposition-friendly designs and provides localized guidance for layout-fixing is presented for double patterning lithography. This methodology uses a library of patterns in which each pattern has been pre-characterized as impossible-to-decompose and annotated with a design rule for guiding the layout fixes. A pattern matching engine identifies these problematic patterns in design, which allows the layout designers to anticipate and prevent decomposition errors, prior to layout decomposition. The methodology has been demonstrated on a 180 um2 layout migrated from the previous 28nm technology node for the metal 1 layer. Using a small library of just 18 patterns, the pattern matching engine identified 119 out of 400 decomposition errors, which constituted coverage of 29.8%.
A Double Patterning Technology (DPT)-aware scoring methodology that systematically quantifies the quality of DPTcompliant
layout designs is described. The methodology evaluates layouts based on a set of DPT-specific metrics that
characterizes layout-induced process variation. Specific metrics include: the spacing variability between two adjacent
oppositely-colored features, the density differences between the two exposure masks, and the stitching area's sensitivity
to mask misalignment. These metrics are abstracted to a scoring scale from 0 to 1 such that 1 is the optimum. This
methodology provides guidance for opportunistic layout modifications so that DPT manufacturability-related issues are
mitigated earlier in design. Results show that by using this methodology, a DPT-compliant layout improved from a
composite score of 0.66 and 0.78 by merely changing the decomposition solution so that the density distribution between
the two exposure masks is relatively equal.
This paper addresses the framework for building critical recommended rules and a methodology for devising scoring
models using simulation or silicon data. Recommended rules need to be applied to critical layout configurations (edge or
polygon based geometric relations), which can cause yield issues depending on layout context and process variability.
Determining of critical recommended rules is the first step for this framework. Based on process specifications and
design rule calculations, recommended rules are characterized by evaluating the manufacturability response to
improvements in a layout-dependent parameter. This study is applied to critical 20nm recommended rules. In order to
enable the scoring of layouts, this paper also discusses a CAD framework involved in supporting use-models for
improving the DFM-compliance of a physical design.
A pattern-based methodology for guiding the generation of DPT-compliant layouts using a foundry-characterized library
of "difficult to decompose" patterns with known corresponding solutions is presented. A pattern matching engine scans
the drawn layout for patterns from the pattern library. If a match were found, one or more DPT-compliant solutions
would be provided for guiding the layout modifications. This methodology is demonstrated on a sample 1.8 mm2 layout
migrated from a previous technology. A small library of 12 patterns is captured, which accounts for 59 out of the 194
DPT-compliance check violations examined. In addition, the methodology can be used to recommend specific changes
to the original drawn design to improve manufacturability. This methodology is compatible with any physical design
flows that use automated decomposition algorithms.
Techniques for identifying and mitigating effects of process variation on the electrical performance of integrated circuits
are described. These results are from multi-discipline, collaborative university-industry research and emphasize
anticipating sources of variation up-stream early in the circuit design phase. The lithography physics research includes
design and testing electronic monitors in silicon at 45 nm and
fast-CAD tools to identify systematic variations for entire
chip layouts. The device research includes the use of a spacer (sidewall transfer) gate fabrication process to suppress
random variability components. The Design-for-Manufacturing research includes double pattern decomposition in the
presence of bimodal CD behavior, process-aware reticle inspection, tool-aware dose trade-off between leakage and
speed, the extension of timing analysis methodology to capture across process-window effects and electrical processwindow
characterization.
Experimental results are reported for ring oscillators (ROs) fabricated using 45nm generation CMOS
technology and inverter layouts that are designed to identify and quantify sources of circuit performance variation
due to gate etch/lithography, gate-to-active misalignment, and CESL-induced stress. The measured RO frequency
data show that within-chip variation is negligible in comparison with chip-to-chip variation. Standard-deviation over mean (σ/μ) values among 36 RO instances show a slight channel area dependence of 0.2% versus sqrt(area)-1.
For a typical wafer, 3% RO frequency change due to gate etch/focus variations, 2-3nm overlay error, and a 5% increase by doubling the length of diffusion (LOD) can be measured.
Parameter-specific and simulation-calibrated ring oscillator (RO) inverter layouts are described for identifying and
quantitatively modeling sources of circuit performance variation from source/drain stress, shallow trench isolation (STI)
stress, lithography, etch, and misalignment. This paper extends the RO approach by adding physical
modeling/simulation of the sources of variability to tune the layouts of monitors for enhanced sensitivity and selectivity.
Poly and diffusion layout choices have been guided by fast-CAD pattern matching. The accuracy of the fast-CAD
estimate from the Pattern Matcher for these lithography issues is corroborated by simulations in Mentor Graphics
Calibre. Generic conceptual results are given based on the experience from preparing of proprietary layouts that pass
DRC check for a 45 nm test chip with ST Micro. Typical improvements in sensitivity of 2 fold are possible with layouts
for lithography focus. A layout monitor for poly to diffusion misalignment based on programmable off-sets shows a
0.8% change in RO frequency per 1nm poly to diffusion off-set. Layouts are also described for characterizing stress
effects associated with diffusion area size, asymmetry, vertical spacing, and multiple gate lengths.
Visualization at the mask plane of the effects of illumination, proximity, and defocus is used to give physical insight into
restricted design rules, layout choices, and residual edge placement errors. To facilitate this work, a pattern matching
code has been tuned, tested, and enhanced. The richness of the original code with complex match factors, mask Boolean
operations, and mask weights and phases has been adapted to operate on clear-field attenuated-phase-shifting masks with
asymmetrical illumination. To account for illumination effects, the aberration spillover is multiplied by the Fourier
transform of the angular distribution of the intensity spectrum incident on the mask. In a study of binary mask layouts,
the R-squared correlation of the prediction of image intensity with Pattern Match Factor increased from 0.57 to 0.89
when annular illumination was included in the spillover function. In addition, features to visualize the mutual
coherence, shifts of the illumination, and source maps have been added.
This paper applies process and circuit simulation to examine plausible explanations for measured differences in ring
oscillator frequencies and to develop layout and electronic circuit concepts that have increased sensitivity to
lithographic parameters. Existing 90nm ring oscillator test chip measurements are leveraged, and the performance
of ring oscillator circuit is simulated across the process parameter variation space using HSPICE and the Parametric
Yield Simulator in the Collaborative Platform for DfM. These simulation results are then correlated with measured
ring oscillator frequencies to directly extract the variation in the underlying parameter. Hypersensitive gate layouts
are created by combining the physical principles in which the effects of illumination, focus, and pattern geometry
interact. Using these principles and parametric yield simulations, structures that magnify the focus effects have been
found. For example, by using 90° phase shift probe, parameter-specific layout monitors are shown to be five times
more sensitive to focus than that of an isolated line. On the design side, NMOS or PMOS-specific electrical
circuits are designed, implemented, and simulated in HSPICE.
Aerial image simulation of interdigitated sidewall capacitor layouts and extraction of feature changes are used to
estimate the parametric performance spread of DC Metal-Oxide-Metal (MOM) mixed signal capacitors as a function of
the normalized lithographic resolution k1. Since minimum feature sizes are utilized, the variation of MOM capacitors is
attributed to lithography spacing. In this paper, k1 of 0.8, 0.56, 0.40, and 0.28 are studied. The DC capacitance shows a
worst-case variability of 42%. While line-end-shortening is a small fractional change in finger length and proves to be
not a critical factor in variability, spacing width proves to be the main source of the variability in DC capacitance.
Different annular illumination settings are explored for mitigating the variability in spacing width. Co-design of the
pitch and illumination shows that for each k1, there is an optimal annular illumination radius. The optimal set of sigmas
(i.e. sigma_in and sigma_out) can control the variability between linewidths and spacing widths to 20%.
This paper proposes a novel method of identifying interactions between neighboring standard cells via fast-CAD pattern
matching. Studies of cell-to-cell interactions for both metal 1 and poly layouts are made for selected samples from
libraries for 130 and 90 nm generations provided under an NDA agreement by ST Microelectronics. Both simulation and
pattern matching are utilized to identify and quantify hot-spots. The physical basis for pattern matching is described. In
validating pattern matching compared to full simulation, changes in linewidth for a fixed defocus setting varied
quadratically with pattern match factor and can be modeled by a parabolic equation with an r-squared value of 0.77.
Results demonstrate that there is a considerable best-to-worst variation of 4-7% in the linewidth among neighbors, which
is produced through a focus swing of 0.58 Rayleigh Units (RU). The focus swing is oscillatory with cell separation
distance, and a slight shift in spacing on the order of 0.5 λ /NA can mitigate lateral interaction effects.
Exploratory prototype DfM tools, methodologies and emerging physical process models are described. The examples
include new platforms for collaboration on process/device/circuits, visualization and quantification of manufacturing
effects at the mask layout level, and advances toward fast-CAD models for lithography, CMP, etch and photomasks. The
examples have evolved from research supported over the last several years by DARPA, SRC, Industry and the Sate of
California U.C. Discovery Program. DfM tools must enable complexity management with very fast first-cut accurate
models across process, device and circuit performance with new modes of collaboration. Collaborations can be promoted
by supporting simultaneous views in naturally intuitive parameters for each contributor. An important theme is to shift
the view point of the statistical variation in timing and power upstream from gate level CD distributions to a more
deterministic set of sources of variations in characterized processes. Many of these nonidealities of manufacturing can be
expressed at the mask plane in terms of lateral impact functions to capture effects not included in design rules. Pattern
Matching and Perturbation Formulations are shown to be well suited for quantifying these sources of variation.
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