Meeting the CD (Critical Dimension) linearity and uniformity targets for high-NA EUV photomasks, requires tight control of a wide range of effects contributing to the distortion of the CD signature. So far, many of the factors degrading CD signature have been optimized independently, in particular the compensation of short- and long-range scattering and etch bias effects. Such independent optimization, however, limits the overall mask CD linearity and uniformity results achievable with co-optimization of the different components.
In this work, we discuss the co-optimization of short- and long-range corrections on the e-beam writer and through MPC (Mask Process Correction).
The use of Inverse Lithography (ILT) in semiconductor manufacturing has been driving the need for curvilinear (CL) mask shapes. CL shapes improve wafer critical dimension (CD) process window through focus, reduce mask error enhancement factor (MEEF) and enable fully utilizing mask rule checker (MRC) specs to guarantee the best OPC correction on challenging corner-to-corner (CTC) and end-to-end (ETE) 2D geometries. The insertion of Multibeam (MBM) writers in mask high volume manufacturing (HVM) enables patterning complex ILT shapes with high CD control and mask fidelity. Additionally, the MBM tool’s capability to use high dose on low sensitivity resist to improve resolution without any write time penalty enables realizing the complex mask shapes from the optical proximity correction (OPC) tool with high accuracy. However more complex CL mask shapes lead to an explosion in the vertex density (vertices/um^2) and file size at the mask shop vs. Manhattan corrections. This talk will review the benefits from CL corrections and present data collected at Intel mask operations (IMO) that outline challenges in processing CL masks through different modules including mask data prep (MDP), beam fracture, inspection and CD Metrology. A path for significant file size reduction with the new MULTIGON record extension to the P39 OASIS file format will be reviewed. MULTIGON insertion involves significant changes in the mask making ecosystem that includes electronic tool design (EDA) tools, MBM writers and inspection tools. A timeline for MULTIGON insertion aligned with the vendors would be reviewed with a goal of enabling MULTIGON in HVM in 2024.
The wafer manufacturing industry has increased pattern complexity of the main feature and sub-resolution assist feature (SRAF) required for improving the EUV lithography process window and enabling the leading-edge technology nodes. In parallel, Inverse Lithography Technology (ILT) and its requirements of curvilinear data structure has gained momentum in recent years, putting the pressure on mask makers, in particular the mask writer. To fulfill the curvilinear feature requirements of high pattern resolution and large data volume, the mask writer needs to develop innovative techniques and update its error compensation strategies. In this paper, we will investigate the pattern resolution, local critical dimension uniformity (LCDU), and line edge roughness (LER) and explore the projected improvements in multi-beam writer technology and highlight its capability against EUV lithography requirements. We will also investigate the role of resist and process on these critical mask metrics to illustrate the overall performance against wafer requirements.
EUV mask exposure tests were conducted at Intel Mask Operation (IMO) on a MBMW201 multi-beam writer to study the effects of writing beam diameter and associate blurs, mask exposure dose, and photoresist on pattern resolution, LCDU, and LER. An analytical model was also used to predict the trend and determine the dependency of these lithographic metrics on the writer exposure conditions.
Multibeam mask writers (MBMW) from IMS Nanofabrication developed in the last decade are currently being used for leading edge mask patterning. The ability to utilize low sensitivity resists required to pattern complex mask patterns with good edge placement control made MBMW the tool of choice for leading edge extreme ultraviolet (EUV) mask patterning. The next generation of High-NA EUV masks will require smaller features, more complex figures and reduction of edge placement errors. These requirements may exceed the capability of the current MBMW tools. Recently IMS announced the next generation MBMW tools to address this challenge. This paper will explore the effectiveness of the proposed improvements on addressing High-NA EUV mask patterning challenges.
EUV lithography requirements continue to present new challenges and opportunities for multi-beam mask writer. Driven by sub-10nm node mask requirements for higher resolution, CD uniformity, pattern placement accuracy, lower line edge roughness (LER), and zero writer-induced defects, the multi-beam mask patterning technology must keep the pace, continue to innovate, and work hand-in-hand with mask makers to overcome these challenges to meet the mask and wafer manufacturing metrics and requirements.
In this paper we will review some of these challenges from the mask maker point of view. Also, we will shed light on a bigger challenge of transitioning to curvilinear mask ILT (Inverse Lithography Technology) data structure and the support needed from multi-beam writer to handle large data volume. Processing and managing this large growth of data helps the mask industry speed up the process of adapting to this technology and enabling EUV mask and wafer manufacturing reach its ultimate goals.
Multi-beam mask writers (MBMW) manufactured by IMS Nanofabrication have been increasingly been accepted into mainstream mask making. Over the past decade, this new class of tools has successfully transitioned from the concept, to development and finally to the production phase. Significant technical challenges specific to the architecture were encountered and overcome. Many of these challenges are related to the large image size used by this writer. In this paper, we will review the motivation to develop this new class of writers and the key technical challenges which had to be overcome to realize lithographic promise. Current status and future opportunities to improve the architecture will be discussed.
Mask writers’ architectures have evolved through the years in response to ever tightening requirements for better resolution, tighter feature placement, improved CD control, and tolerable write time. The unprecedented extension of optical lithography and the myriad of Resolution Enhancement Techniques have tasked current mask writers with ever increasing shot count and higher dose, and therefore, increasing write time. Once again, we see the need for a transition to a new type of mask writer based on massively parallel architecture. These platforms offer a step function improvement in both dose and the ability to process massive amounts of data. The higher dose and almost unlimited appetite for edge corrections open new windows of opportunity to further push the envelope. These architectures are also naturally capable of producing curvilinear shapes, making the need to approximate a curve with multiple Manhattan shapes unnecessary.
Mask patterning capability continues to be a key enabler for wafer patterning. Mask writer performance is critical to meet reticle resolution, critical dimension uniformity, registration, and throughput requirements. Technology trends indicate that mask requirements will require higher dose resists with more complex designs producing write time growth that significantly exceeds Moore’s law estimates. Sub 10 nm technology node requirements may exceed what is practically or economically achievable using conventional single beam writers. This is driving the need to explore alternative e-beam mask writer architectures for future nodes.
Several equipment suppliers are proposing new architectures for mask patterning. These approaches share the characteristic of some level of parallelism to solve the throughput challenge caused by increasing mask pattern complexity. Although parallelism is a proven approach in laser mask writers, it has not been integrated into an e-beam platform. All of the approaches for multibeam e-beam architectures have unique technical difficulties. In some cases, suppliers have produced proof of concept results to demonstrate the feasibility of their approach and address key technical risks. Although these results are encouraging, it is clear that they need more time and industry assistance to produce a commercially worthy mask writer.
Key drivers will be considered. Proposed evolutionary extensions of the current architecture will be evaluated. The need for revolutionary architectures to satisfy future mask patterning will be explored.
A significant barrier to implementing APSM in volume production has been the expense of the mask. The cost of the
mask is driven partially by the complexity of the two layer process flow required to make the mask. Typically, the 2nd
level pattern is generated by upsizing the first level pattern of the pi apertures by a small amount in order to provide
some overlay margin. The amount of upsizing is limited by the smallest chrome feature present in the pattern. The
overlay margin between the first and 2nd level patterns can be improved by sizing the 2nd level more on larger chrome
structures, when present. With a simple set of rules, it is possible to generate a 2nd level pattern with greater than ten
times reduction in the number of corners, as measured by the number of vertices in the pattern, and minimize the number
of marginal patterns in the design. This also has the beneficial side effect of significantly reducing the file size of the 2nd
level pattern which can reduce the write time on some writers. Existing design rules can be exploited or additional rules
imposed that can further improve the capability of the 2nd level APSM process. The right set of mask design rules can
enable the use of lower fidelity writer for 2nd level patterning which can significantly reduce cost. The improved margin
can increase yield and may even enable a less capable/expensive patterning tool to be used for 2nd level patterning.
Aggressive 193nm optical lithography solutions have in turn led to increasingly complex model-based OPC methodologies. This complexity married with the inevitable march of Moore's Law has produced a figure count explosion at the mask writer level. Variable shaped beam equipment manufacturers have tried to mollify the impact of this figure count explosion on the write time by the introduction of new technologies such as increased beam current density, faster DAC amplifiers and more efficient stage algorithms. Despite these efforts, mask manufacturers continue to explore ways of increasing writer throughput and available capacity. This study models the impact of further improvements in beam current density and settling times. Furthermore, this model will be used to prescribe the necessary improvement rates needed to keep pace with the shot count trends extending beyond the 45nm node.
Alternating phase shift mask (APSM) techniques help bridge the significant gap between the lithography wavelength and the patterning of minimum features, specifically, the poly line of 35 nm gate length (1x) in Intel's 65 nm technology. One of key steps in making APSM mask is to pattern to within the design tolerances the 2nd level resist so that the zero-phase apertures will be protected by the resist and the pi-phase apertures will be wide open for quartz etch. The ability to align the 2nd level to the 1st level binary pattern, i.e. the 2nd level overlay capability is very important, so is the capability of measuring the overlay accurately. Poor overlay could cause so-called the encroachment after quartz etch, producing undesired quartz bumps in the pi-apertures or quartz pits in the zero-apertures. In this paper, a simple, low-cost optical setup for the 2nd level DC (develop check) overlay measurements in the high volume manufacturing (HVM) of APSM masks is presented. By removing systematic errors in overlay associated with TIS and MIS (tool-induced shift and Mask-process induced shift), it is shown that this setup is capable of supporting the measurement of DC overlay with a tolerance as small as +/- 25 nm. The outstanding issues, such as DC overlay error component analysis, DC - FC (final check) overlay correlation and the overlay linearity (periphery vs. indie), are discussed.
SLM-based DUV laser writers are gaining acceptance for 2nd level PSM and binary mask patterning. These writers can use an e-beam compatible resist enabling tool and process sharing. For binary mask patterning, critical metrics include: critical dimension uniformity (CDU), CD targeting, mask registration, defect performance and inspectability. For PSM applications, pattern fidelity matching to 1st level and PSM overlay are also important. A Sigma7300 is being integrated into 65nm and 45nm production. Binary and PSM mask performance data will be presented. Tool self metrics to characterize SLM health will also be presented. Data conversion, data preparation and production write times will be discussed.
Phase shift mask (PSM) applications are becoming essential for addressing the lithography requirements of the 65 nm technology node and beyond. Many mask writer properties must be under control to expose the second level of advanced PSM: second level alignment system accuracy, resolution, pattern fidelity, critical dimension (CD) uniformity and registration. Optical mask writers have the advantage of process simplicity for this application, as they do not require a discharge layer. This paper discusses how the mask writer properties affect the error budget for printing the second level. A deep ultraviolet (DUV) mask writer with a spatial light modulator (SLM) is used in the experimental part of the paper. Partially coherent imaging optics at the 248 nm wavelength provide improved resolution over previous systems, and pattern fidelity is optimized by a real-time corner enhancement function. Lithographic performance is compared to the requirements for second level exposure of advanced PSM. The results indicate sufficient capability and stability for 2nd level alternating PSM patterning at the 65 nm and 45 nm nodes.
Tighter lithography requirements are increasing the challenges for mask registration metrology. Demands on calibration will increase as tool specific calibration need to significantly improve to enable accurate plate quality assessment and adequate matching between multiple writer and metrology system. We present results of calibration study conducted on Leica LMS IPRO 2 and LMS IPRO1. Two different calibration techniques were used to match the tool grid to absolute Cartesian coordinate system. The impact of the two calibration techniques on tool matching is summarized. The results are used to make recommendations on improving calibration methodology.
Multiphase printing (MPPTM) has been shown to improve registration and CD performance by reducing butting errors, averaging scan linearity errors and improving stripe boundary CD performance. In the MEBES 4500, improvements in the data path allow MPP to be used with a tolerable increase in write time making it an attractive option. A major concern is determining if MPP printing requires modification of subsequent mask processing steps. The use of larger spot sizes and multiple voting in MPP printing may alter CD performance during mask processing. Additionally, the multipass strategy inherent to MPP could result in a different CD signature due to time based effects. A further concern is to determine if MPP CD's impact pattern fidelity since this will affect inspectibility and wafer performance. Several experiments were conducted to determine how well MPP integrates with processing, how it is impacted by temporal averaging of errors and if it significantly alters pattern fidelity. A range of input addresses and different resist systems were investigated.
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