Polarization dependent diffraction efficiencies in transmission through gratings on specially designed masks with pitch comparable to the wavelength were measured using an angle-resolved scatterometry apparatus with a 193 nm excimer source. Four masks - two binary, one alternating and one attenuated phase shift mask - were included in the experimental measurements. The validity of models used in present commercially available simulation packages and additional polarization effects were evaluated against the experimental scattering efficiencies.
Phase shift techniques introduced in photolithography to further improve resolution produce a new set of challenges for inspection. Unlike the high contrast provided by patterned and unpatterned areas on a binary mask, phase errors do not provide significant contrast changes, since the phase change is imparted by a difference in material thickness. Surface topology measurements can be used to identify phase defects, but methods for surface topology inspection are typically slow or can damage the surface to be measured. In this study, Spatial Heterodyne Interferometry (SHI) has been considered as a possible method for high-speed non-contact phase defect detection. SHI is an imaging technique developed at Oak Ridge National Laboratory that acquires both phase and amplitude information from an optical wavefront with a single high-speed image capture. Using a reflective SHI system, testing has been performed with a mask containing programmed phase defects of various sizes and depths. In this paper, we present an overview of the SHI measurement technique, discuss issues such as phase wrapping associated with using SHI for phase defect detection on photolithographic masks, and present phase defect detection results from die-to-die comparisons on a 248 nm alternating aperture phase shift mask with intentional phase defects.
Binary and phase-shifting chromium on quartz optical photomasks have been successfully investigated with high-pressure/environmental scanning electron microscopy (SEM). The successful application of this methodology to semiconductor photomask metrology is new because of the recent availability of high-pressure SEM instrumentation equipped with high-resolution, high-signal, field emission technology in conjunction with large chamber and sample transfer capabilities. The high-pressure SEM methodology employs a gaseous environment to help diminish the charge buildup that occurs under irradiation with the electron beam. Although very desirable for charge reduction, this methodology has not been employed in production photomask or wafer metrology until now. This is a new application of this technology to this area, and it shows great promise in the inspection, imaging and metrology of photomasks in a charge-free operational mode. This methodology also holds the potential of similar implications for wafer metrology. For accurate metrology, high-pressure SEM methodology also affords a path that minimizes, if not eliminates, the need for charge modeling. This paper presents some new results in high-pressure SEM metrology of photomasks.
Photomask dimensional metrology in the scanning electron microscope has not evolved as rapidly as the metrology of resists and integrated circuit features on wafers. This has been due partly to the 4× (or 5×) reduction in optical steppers and scanners used in the lithography process, and partly for the lesser need to account for the real three dimensionality of the mask structures. So, where photomasks are concerned, many of the issues challenging wafer dimensional metrology at 1× are reduced by a factor of 4 or 5 and thus could be temporarily swept aside. This is rapidly changing with the introduction of advanced masks with optical proximity correction and phase shifting features used in 100 nm and smaller circuit generations. Fortunately, photomask metrology generally benefits from the advances made for wafer metrology, but there are still unique issues to be solved in this form of dimensional metrology. It is likely that no single metrology method or tool will ever provide all necessary answers. As with other types of metrology, resolution, sensitivity and linearity in three-dimensional measurements of the shape of the lines and phase shifting features in general (width, height and wall angles) and departure from the desired shape (surface and edge roughness, etc.) are the key parameters. Different methods and tools differ in their capability to collect average and localized signals at acceptable speed, but in any case, application of thorough knowledge of the physics of the given metrology is essential to extract the information needed. This paper will discuss the precision, accuracy and traceability in SEM metrology of photomasks. Current and possible new techniques utilized in the measurements of photomasks including suppression of charge and highly accurate modeling for electron beam metrology will also be explored to answer the question, Has anything really changed?
Spatial heterodyne interferometry (SHI) is an imaging technique that captures both the phase and amplitude of a complex wavefront in a single high-speed image. This technology was developed at the Oak Ridge National Laboratory (ORNL) and is currently being implemented for semiconductor wafer inspection by nLine Corporation. As with any system that measures phase, metrology and inspection of surface structures is possible by capturing a wavefront reflected from the surface. The interpretation of surface structure heights for metrology applications can become very difficult with the many layers of various materials used on semiconductor wafers, so inspection (defect detection) has been the primary focus for semiconductor wafers. However, masks used for photolithography typically only contain a couple well-defined materials opening the doors to high-speed mask metrology in 3 dimensions in addition to inspection. Phase shift masks often contain structures etched out of the transparent substrate material for phase shifting. While these structures are difficult to inspect using only intensity, the phase and amplitude images captured with SHI can produce very good resolution of these structures. The phase images also provide depth information that is crucial for these phase shift regions.
Preliminary testing has been performed to determine the feasibility of SHI for high-speed non-contact mask metrology using a prototype SHI system with 532 nm wavelength illumination named the Visible Alpha Tool (VAT). These results show that prototype SHI system is capable of performing critical dimension measurements on 400nm lines with a repeatability of 1.4nm and line height measurements with a repeatability of 0.26nm. Additionally initial imaging of an alternating aperture phase shift mask has shown the ability of SHI to discriminate between typical phase shift heights.
In semiconductor device manufacturing, critical dimension (CD) metrology provides a measurement for precise line-width control during the lithographic process. Currently scanning electron microscope (SEM) tools are typically used for this measurement, because the resolution requirements for the CD measurements are outside the range of optical microscopes. While CD has been a good feedback control for the lithographic process, line-widths continue to shrink and a more precise measurement of the printed lines is needed. With decreasing line widths, the entire sidewall structure must be monitored for precise process control. Sidewall structure is typically acquired by performing a destructive cross sectioning of the device, which is then imaged with a SEM tool. Since cross sectioning is destructive and slow, this is an undesirable method for testing product wafers and only a small sampling of the wafers can be tested. We have developed a technique in which historical cross section/top down image pairs are used to predict sidewall shape from top down SEM images. Features extracted from a new top down SEM image are used to locate similar top downs within the historical database and the corresponding cross sections in the database are combined to create a sidewall estimate for the new top down. Testing with field test data has shown the feasibility of this approach and that it will allow CD SEM tools to provide cross section estimates with no change in hardware or complex modeling.
International SEMATECH (ISMT) and the National Institute of Standards and Technology (NIST) are working together to improve the traceability of atomic force microscope (AFM) dimensional metrology in semiconductor manufacturing. The rapid pace of technological change in the semiconductor industry makes the timely introduction of relevant standards challenging. As a result, the link between the realization of the SI (Systeme International d’Unites, or International System of Units) unit of length - the meter - and measurements on the fab line is not always maintained. To improve this situation, we are using an at-line critical dimension-AFM (CD-AFM) at ISMT as a developmental platform. This tool has been implemented as a Reference Measurement System (RMS) in the facilities at ISMT. However, it is currently being replaced by a next-generation CD-AFM tool. Using the current tool, we have performed measurements needed to establish the traceability chain and developed uncertainty budgets. Specifically, we have developed uncertainty budgets for pitch, height, and critical dimension (CD) measurements. Some evaluations were performed using samples for which a full traceability chain is not available. We expect to improve the uncertainties further for such samples. At present, the standard uncertainties are estimated to be approximately 0.2 % for pitch measurements, 0.4 % for step height measurements, and 5 nm for CD measurements in the sub-micrometer range. Similar budgets will be developed for the new tool once it is installed. We will describe our methodology for RMS implementation and the major applications for which it has been used. These include measurements on new NIST/ISMT linewidth standards, a reference tool for CD-scanning electron microscopes (SEMs), metrology on photo-masks, CD-SEM benchmarking, and 193 nm resist shrinkage measurements.
Photomask dimensional metrology in the scanning electron microscope (SEM) has not evolved as rapidly as the metrology of resists and integrated circuit features on wafers. This has been due partly to the 4x (or 5x) reduction in the optical steppers and scanners used in the lithography process, and partly for the lesser need to account for the real three-dimensionality of the mask structures. So, where photomasks are concerned, many of the issues challenging wafer dimensional metrology at 1x are reduced by a factor of 4 or 5 and thus could be temporarily swept aside. This is rapidly changing with the introduction of advanced masks with optical proximity correction and phase shifting features used in 100 nm and smaller circuit generations.
Fortunately, photomask metrology generally benefits from the advances made for wafer metrology, but there are still unique issues to be solved in this form of dimensional metrology. It is likely that no single metrology method or tool will ever provide all necessary answers. As with other types of metrology, resolution, sensitivity and linearity in the three-dimensional measurements of the shape of the lines and phase shifting features in general (width, height and wall angles) and the departures from the desired shape (surface and edge roughness, etc.) are the key parameters. Different methods and tools differ in their ability to collect averaged and localized signals with an acceptable speed, but in any case, application of this thorough knowledge of the physics of the given metrology is essential to extract the needed information. This paper will discuss the topics of precision, accuracy and traceability in the SEM metrology of photomasks. Current and possible new techniques utilized in the measurements of photomasks including charge suppression and highly accurate modeling for electron beam metrology will also be explored to answer the question “Has anything really changed?”
The in-line and at-line measurement tools for critical dimension (CD) metrology in semiconductor manufacturing are technologically advanced instruments that exhibit excellent measurement repeatability - below one nanometer in some cases. Accuracy, however, is largely dependent upon the availability of traceable standards. Because the standards requirements of this fast-paced industry are particularly demanding and application-specific, metrology traceability is sometimes lacking. International SEMATECH (ISMT) and the National Institute of Standards and Technology (NIST) are working together to improve this situation. We are developing a reference measurement system (RMS) at ISMT using a critical-dimension atomic force microscope (CD-AFM). We are performing measurements needed to establish the traceability chain and develop uncertainty budgets for this tool. Monitoring of tool performance has been improved and we have performed preliminary checks of lateral and vertical scale calibration. Preliminary uncertainty budgets for pitch and height measurements have been developed. At present, the standard uncertainty due to scale calibration and non-linearity is estimated to be approximately 0.2 percent for pitch measurements and 0.5 percent for step height measurements. Our initial checks of scale calibration were performed using samples for which a full traceability chain is not available. We expect to reduce these uncertainties once we are able to use samples with a complete traceability chain. Ultimately, our major objective in developing an RMS is to provide a traceable metrology reference for other major projects at ISMT - including CD-SEM benchmarking, AMAG wafer development, and overlay tool benchmarking.
KEYWORDS: Semiconducting wafers, Calibration, Etching, Critical dimension metrology, Scanning electron microscopy, Lithography, Line edge roughness, Cadmium, Error analysis, Process control
One goal of CD metrology is to monitor lithographic process control and how it relates to post-etch results. At present, in-fab process control for this purpose is achieved through top-done CD measurements. To acquire profile information requires destructive cross-section SEM measurements or time- consuming atomic force microscope (AFM) measurements. To find height and profile information about a resist or etched structure directly on a CD-SEM, new techniques using the combination of in-column beam tilt and stereo graphic imaging have been developed and implemented on the Applied Materials VeraSEM-3D.
Prototype linewidth reference materials with Critical Dimensions (CDs) as narrow as 70 nm have been patterned in silicon-on-insulator films. The sidewalls of the reference features are parallel, normal to the substrate surface, and have almost atomically smooth surfaces. Linewidth calibration begins with the measurement of the electrical CDs of multiple reference features located at a selection of die sites on a wafer. The absolute widths of the cross sections of a sub-set of reference features on several chips that are diced from the wafer are then subjected to high resolution transmission electron microscopy (HRTEM) imaging to determine their physical CDs by lattice-plane counting. Sample preparation for lattice-plane counting by HRTEM Is destructive, and other reference features on the same chip become unusable for reference-material purposes. However, a calibration curve for converting the measured electrical CDs of reference features on other chips on the wafer, known as 'product reference features', to their physical values is obtained. The uncertainty attributed to the physical CD values of the product reference features generally varies inversely with the linear correlation between the cross- section lattice-plane counts and the corresponding electrical CD measurements of the sub-set of reference features that were selected for HRTEM imaging. A linear correlation value of approximately 0.97 has been obtained from a sub-set of 12 HRTEM measurements. In this case, the uncertainty attributed to the physical CD values of the product reference features is believed to be responsible for most of the product reference feature uncertainty. However, it has now been found that a forming-gas annealing treatment appears to prevent the referenced time dependence and thus has the potential for reducing the uncertainty level.
A portion of the mission of the NIST Manufacturing Engineering Laboratory is to improve and advance length metrology in aid of US industry. The successful development of a 'collaboratory' for telepresence microscopy technology. Telepresence microscopy is an advanced concept in the integration of computers and high-speed networks with scientific instruments for operation. Control, communication and research. NIST and TI, under the auspices of the National Automated Manufacturing Testbed and in collaboration with the University of Illinois and Argonne National Laboratory have developed a collaboratory testbed. The goal of this work is to demonstrate the value of TPM within organization having a large distributed manufacturing facility such as TI and between scientific research organizations such as NIST, ANL and UIC. Large distributed manufacturing sites need rapid response when problems threaten to disrupt multi-million dollar production facilities. This is particularly important when expertise needed to solve the problem or instrumentation is not locally present. The resulting delays are inevitable and often costly. Telepresence minimizes these delays. Once a sample has been received by a research facility, collaborators from multiple remotely located sites can rapidly access the collaboratory from their respective locations and collaborate in real-time to solve the problem using only their desktop computers and connections to the Internet. This presentation demonstrates the power afforded by this technology.
Automation tools for semiconductor defect data analysis are becoming necessary as device density and wafer sizes continue to increase. These tools are needed to efficiently and robustly process the increasing amounts of data to quickly characterize manufacturing processes and accelerate yield learning. An image-based method is presented for analyzing process 'signatures' from defect data distributions. This paper describes the statistical and morphological image processing methods used to achieve an automated segmentation of signature events into high-level process-oriented categories. Applications are presented for enhanced statistical process control, automatic process characterization, and intelligent subsampling of event distributions for off-line, high-resolution defect review.
An advanced in-line patterned wafer defect detection system has been developed in a Joint Development Project (JDP) with Tencor Instruments and SEMATECH. The JDP, known as J101, was initiated due to critical needs identified in a SEMATECH Phase 4/5 (0.25 micrometers ) Workshop. The goal of the workshop was to identify the most suitable and cost-effective technology to meet the in-line monitoring needs specified in the National Technology Roadmap for Semiconductors (NTRS), also known as the SIA technology roadmap. This paper will review the inspection requirements identified in the SEMATECH Phase 4/5 (0.25 micrometers ) Workshop, specify the objectives and milestones of the JDP, provide a technology overview of the system, and show results obtained by using the system during alpha and prototype characterization.
As device geometries shrink to 0.25 micron and smaller, all facets of integrated circuit (IC) processing are being challenged. With device sizes shrinking, so too shrinks the size of a defect that can cause chip failure, and hence yield loss. Contamination free manufacturing practices are becoming critical for successful device fabrication. To accomplish this, elimination of defect sources has a high priority. A defect can be a particle, microcontamination, pattern anomaly, crystalline defect such as a stacking fault, and so on. Defects have become a main source of yield loss to the semiconductor industry. This comes at a time when 90% yield values on mature product cannot increase at the rate that has occurred in the past. The industry is now faced with finding methods of incremental yield increase, in-line, on production wafers. Automatic Defect Classification (ADC) is an important part of SEMATECH's strategy to meet these industry needs.
Particles, defects, and microcontaminaton: the bane of the IC process engineer! Controlling defects during every processing step of semiconductor devices is vital to successful manufacturing of modem chips. The requirements for tight defect control become increasingly severe with each new generation of semiconductors. For a typical 16 MB DRAM process, the total number of defects must be less than one for each 4 cm2 Gf Wafer surface area in order to achieve 70% yield on the wafer.1 Not only must the total number of defects on wafers decrease with each generation, the defect concentration per mask level must be reduced at an ever faster rate due to higher circuit complexity and increased number of mask levels. These defect reduction requirements are noted here for DRAMs, used as the technology driver, but must also be achieved in other device families such as ASICs and microprocessors.
A variety of techniques are currently in use for process monitoring and control of wafer quality during production. In general these techniques fall into two categories: (1) particle monitors that provide fast, simple results but are limited in visibility to many defects, and (2) more advanced systems that monitor a much larger class of potential problems but require significant analysis time and interpretation of results. The first category has traditionally been used for in-line monitoring, while the second category has served primarily for engineering analysis and R&D applications. Recent technical developments, in particular the development of advanced systems based on optical pattern filtering, have begun to blur the distinction between in-line and engineering analysis tools. This paper establishes performance guidelines for in-line process monitoring tools, reviews the current techniques utilized against these guidelines, and discusses the potential applications of these methods to in-line process control. Systems based on these new techniques hold the promise of providing sophisticated analysis capability for in-line process control applications, by offering extremely high throughput (in the range of a few minutes per wafer) and high sensitivity (0.20 micrometers and better), combined with intelligent but fully automated analysis of the data to provide `single-number' reports on production wafers.
It is estimated that by the year 1995, as much as ninety percent of the contamination in IC manufacturing will be caused by equipment and processes. Contamination can be in the form of particles, defects, scratches, stains, and so on. All are major concerns for yielding ULSI devices. In order to eliminate process/equipment-induced particles, particle formation/generation must be understood before appropriate action can be taken to meet the contamination-free requirements of the future. A variety of vacuum processing tools were studied, including CVD, PECVD, and plasma etch systems with heat lamps, RF, and remote microwave energy sources. A particle collection and characterization methodology was adopted to analyze the particles generated from the vacuum processing tools. By using SEM and EDS to analyze particles collected from equipment chamber walls, both the particle morphology and composition were discerned. The elemental analyses indicate that the composition of particles varied a great deal depending on the chemical nature of the process, chamber material/process compatibility, and energy source.
A wafer metrology 'round robin' has been completed comparing linewidth measurements from several different companies and different measurement tools and technologies. The project has been conducted under the auspices of SEMI by members of SEMI's Metrology Committee. The goals of the program were: (1) determine the range of critical dimension values measured across the United States, (2) test the newly formulated SEMI linewidth patterns, (3) assess the effect of calibration differences of the measured values.
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