Mr. Masahiro Yamamoto Profile

Masahiro Yamamoto

President and Chief Executive Officer at TASMIT Inc

SPIE Involvement:

Author

Publications (18)

Proceedings Article | 19 March 2015 Paper

Paper

Advanced overlay analysis through design based metrology

Sunkeun Ji, Gyun Yoo, Gyoyeon Jo, Hyunwoo Kang, Minwoo Park, Jungchan Kim, Chanha Park, Hyunjo Yang, Donggyu Yim, Kotaro Maruyama, Byungjun Park, Masahiro Yamamoto

Proceedings Volume 9424, 942415 (2015) https://doi.org/10.1117/12.2085464

KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Data analysis, Etching, Optical lithography, Double patterning technology, Imaging systems, Error analysis, Distortion

Read Abstract +

Proceedings Article | 2 April 2014 Paper

Paper

Real cell overlay measurement through design based metrology

Gyun Yoo, Jungchan Kim, Chanha Park, Taehyeong Lee, Sunkeun Ji, Gyoyeon Jo, Hyunjo Yang, Donggyu Yim, Masahiro Yamamoto, Kotaro Maruyama, Byungjun Park

Proceedings Volume 9050, 90501O (2014) https://doi.org/10.1117/12.2046294

KEYWORDS: Overlay metrology, Semiconducting wafers, Metrology, Computer aided design, Manufacturing, Inspection, Scanning electron microscopy, Image processing, Data processing, Metals

Read Abstract +

Until recent device nodes, lithography has been struggling to improve its resolution limit. Even though next generation lithography technology is now facing various difficulties, several innovative resolution enhancement technologies, based on 193nm wavelength, were introduced and implemented to keep the trend of device scaling. Scanner makers keep developing state-of-the-art exposure system which guarantees higher productivity and meets a more aggressive overlay specification. “The scaling reduction of the overlay error has been a simple matter of the capability of exposure tools. However, it is clear that the scanner contributions may no longer be the majority component in total overlay performance. The ability to control correctable overlay components is paramount to achieve the desired performance.(2)” In a manufacturing fab, the overlay error, determined by a conventional overlay measurement: by using an overlay mark based on IBO and DBO, often does not represent the physical placement error in the cell area of a memory device. The mismatch may arise from the size or pitch difference between the overlay mark and the cell pattern. Pattern distortion, caused by etching or CMP, also can be a source of the mismatch. Therefore, the requirement of a direct overlay measurement in the cell pattern gradually increases in the manufacturing field, and also in the development level. In order to overcome the mismatch between conventional overlay measurement and the real placement error of layer to layer in the cell area of a memory device, we suggest an alternative overlay measurement method utilizing by design, based metrology tool. A basic concept of this method is shown in figure1. A CD-SEM measurement of the overlay error between layer 1 and 2 could be the ideal method but it takes too long time to extract a lot of data from wafer level. An E-beam based DBM tool provides high speed to cover the whole wafer with high repeatability. It is enabled by using the design as a reference for overlay measurement and a high speed scan system. In this paper, we have demonstrated that direct overlay measurement in the cell area can distinguish the mismatch exactly, instead of using overlay mark. This experiment was carried out for several critical layer in DRAM and Flash memory, using DBM(Design Based Metrology) tool, NGR2170™.

Proceedings Article | 18 April 2013 Paper

Paper

Application of DBM tool for detection of EUV mask defect

Gyun Yoo, Jungchan Kim, Chanha Park, Taehyeong Lee, Sunkeun Ji, Hyunjo Yang, Donggyu Yim, Byeongjun Park, Kotaro Maruyama, Masahiro Yamamoto

Proceedings Volume 8681, 868121 (2013) https://doi.org/10.1117/12.2011476

KEYWORDS: Photomasks, Inspection, Wafer inspection, Semiconducting wafers, Metals, Extreme ultraviolet, Extreme ultraviolet lithography, Metrology, Defect inspection, Lithography

Read Abstract +

Proceedings Article | 5 April 2012 Paper

Paper

Application of DBM system to overlay verification and wiggling quantification for advanced process

Taehyeong Lee, Jungchan Kim, Gyun Yoo, Chanha Park, Hyunjo Yang, Donggyu Yim, Byoungjun Park, Kotaro Maruyama, Masahiro Yamamoto

Proceedings Volume 8324, 83241B (2012) https://doi.org/10.1117/12.916110

KEYWORDS: Overlay metrology, Semiconducting wafers, Inspection, Process control, Metrology, Semiconductors, Etching, Array processing, Control systems, Line edge roughness

Read Abstract +

Proceedings Article | 20 April 2011 Paper

Paper

OPC verification and hotspot management for yield enhancement through layout analysis

Gyun Yoo, Jungchan Kim, Taehyeong Lee, Areum Jung, Hyunjo Yang, Donggyu Yim, Sungki Park, Kotaro Maruyama, Masahiro Yamamoto, Abhishek Vikram, Sangho Park

Proceedings Volume 7971, 79710H (2011) https://doi.org/10.1117/12.870395

KEYWORDS: Optical proximity correction, Semiconducting wafers, Image classification, Transistors, Manufacturing, Tolerancing, Optical lithography, Inspection, OLE for process control, Semiconductors

Read Abstract +

Proceedings Article | 2 April 2010 Paper

Paper

Systematic and random defects control with design-based metrology

Hyunjo Yang, Jungchan Kim, Taehyeong Lee, Areum Jung, Gyun Yoo, Donggyu Yim, Sungki Park, Toshiaki Hasebe, Masahiro Yamamoto

Proceedings Volume 7638, 76380I (2010) https://doi.org/10.1117/12.846739

KEYWORDS: Inspection, Defect detection, Metrology, Control systems, Semiconducting wafers, Process control, Computer aided design, Design for manufacturing, Bridges, Resolution enhancement technologies

Read Abstract +

Proceedings Article | 14 December 2009 Paper

Paper

Hot spot management through design based metrology: measurement and filtering

Taehyeong Lee, Hyunjo Yang, Jungchan Kim, Areum Jung, Gyun Yoo, Donggyu Yim, Sungki Park, Akio Ishikawa, Masahiro Yamamoto, Abhishek Vikram

Proceedings Volume 7520, 75201U (2009) https://doi.org/10.1117/12.837228

KEYWORDS: Optical proximity correction, Metrology, Semiconducting wafers, Inspection, Metals, Error analysis, Process control, OLE for process control, Design for manufacturing, Electronic design automation

Read Abstract +

Proceedings Article | 24 March 2009 Paper

Paper

Systematic defect filtering and data analysis methodology for design based metrology

Hyunjo Yang, Jungchan Kim, Taehyeong Lee, Areum Jung, Gyun Yoo, Donggyu Yim, Sungki Park, Toshiaki Hasebe, Masahiro Yamamoto, Jun Cai

Proceedings Volume 7272, 72721C (2009) https://doi.org/10.1117/12.814373

KEYWORDS: Computer aided design, Metrology, Semiconducting wafers, Electronic design automation, Metals, Inspection, Optical proximity correction, Data analysis, Error analysis, Design for manufacturing

Read Abstract +

Proceedings Article | 4 December 2008 Paper

Paper

The APC (Advanced Process Control) procedure for process window and CDU improvement using DBMs

Jung-Chan Kim, Taehyeong Lee, Areum Jung, Gyun Yoo, Hyunjo Yang, Donggyu Yim, Sungki Park, Jaeyoung Seo, Byoungjun Park, Toshiaki Hasebe, Masahiro Yamamoto

Proceedings Volume 7140, 71403G (2008) https://doi.org/10.1117/12.804652

KEYWORDS: Semiconducting wafers, Inspection, Photomasks, Critical dimension metrology, Metrology, Computer aided design, Process control, Yield improvement, Design for manufacturing, Scanning electron microscopy

Read Abstract +

Proceedings Article | 1 April 2008 Paper

Paper

A new robust process window qualification (PWQ) technique to perform systematic defect characterization to enlarge the lithographic process window using a die-to-database verification tool (NGR2100)

Tadashi Kitamura, Toshiaki Hasebe, Kazufumi Kubota, Futoshi Sakai, Shinichi Nakazawa, Michael Hoffman, Masahiro Yamamoto, Masahiro Inoue

Proceedings Volume 6925, 692519 (2008) https://doi.org/10.1117/12.772706

KEYWORDS: Lithography, Inspection, Optical proximity correction, Defect detection, Bridges, Optical inspection, Scanning electron microscopy, Semiconducting wafers, Semiconductors, Design for manufacturability

Read Abstract +

Proceedings Article | 25 March 2008 Paper

Paper

Wide applications of design based metrology with tool integration

Hyunjo Yang, Jungchan Kim, Areum Jung, Taehyeong Lee, Donggyu Yim, Jinwoong Kim, Toshiaki Hasebe, Masahiro Yamamoto

Proceedings Volume 6922, 692239 (2008) https://doi.org/10.1117/12.772664

KEYWORDS: Semiconducting wafers, Optical proximity correction, Computer aided design, Electronic design automation, Metrology, OLE for process control, Process control, Transistors, Design for manufacturing, Data analysis

Read Abstract +

Proceedings Article | 5 April 2007 Paper

Paper

Advanced process control with design-based metrology

Hyunjo Yang, Jungchan Kim, Jongkyun Hong, Donggyu Yim, Jinwoong Kim, Toshiaki Hasebe, Masahiro Yamamoto

Proceedings Volume 6518, 651821 (2007) https://doi.org/10.1117/12.712051

KEYWORDS: Semiconducting wafers, Optical proximity correction, Computer aided design, Overlay metrology, Process control, Inspection, Design for manufacturing, Resolution enhancement technologies, Metrology, Critical dimension metrology

Read Abstract +

Proceedings Article | 5 April 2007 Paper

Paper

Die-to-database verification tool for detecting CD errors, which are caused by OPC features, by using mass gate measurement and layout information

Tadashi Kitamura, Toshiaki Hasebe, Kazufumi Kubota, Futoshi Sakai, Shinichi Nakazawa, David Lin, Michael Hoffman, Masahiro Yamamoto, Masahiro Inoue

Proceedings Volume 6518, 651834 (2007) https://doi.org/10.1117/12.712413

KEYWORDS: Critical dimension metrology, Error analysis, Optical proximity correction, Statistical analysis, Inspection, Computer aided design, Optical design, Photomasks, Scanning electron microscopy, Semiconducting wafers

Read Abstract +

Proceedings Article | 21 March 2007 Paper

Paper

OPC and design verification for DFM using die-to-database inspection

JungChan Kim, HyunJo Yang, JooKyoung Song, DongGgyu Yim, JinWoong Kim, Toshiaki Hasebe, Masahiro Yamamoto

Proceedings Volume 6521, 652117 (2007) https://doi.org/10.1117/12.711348

KEYWORDS: Critical dimension metrology, Optical proximity correction, Error analysis, Inspection, Design for manufacturing, Computer aided design, Lithography, Semiconducting wafers, Databases, Statistical analysis

Read Abstract +

Proceedings Article | 20 October 2006 Paper

Paper

Introduction of a die-to-database verification tool for mask geometry NGR4000

Michael Hoffman, Tadashi Kitamura, Kazufumi Kubota, Toshiaki Hasebe, Shinichi Nakazawa, Toshifumi Tokumoto, Masatoshi Tsuneoka, Masahiro Yamamoto, Masahiro Inoue

Proceedings Volume 6349, 634940 (2006) https://doi.org/10.1117/12.684984

KEYWORDS: Photomasks, Scanning electron microscopy, Critical dimension metrology, Distortion, Inspection, Metrology, Optical proximity correction, Optical inspection, Error analysis, Electron microscopes

Read Abstract +

Proceedings Article | 20 October 2006 Paper

Paper

Direct die-to-database electron-beam inspection of fused silica imprint templates

M. Tsuneoka, T. Hasebe, T. Tokumoto, C. Yan, M. Yamamoto, D. Resnick, E. Thompson, H. Wakamori, M. Inoue, Eric Ainley, Kevin Nordquist, William Dauksher

Proceedings Volume 6349, 63492D (2006) https://doi.org/10.1117/12.687196

KEYWORDS: Inspection, Silica, Semiconducting wafers, Metals, Lithography, Scanning electron microscopy, Photomasks, Chromium, Logic, Etching

Read Abstract +

Proceedings Article | 28 June 2005 Paper

Paper

Introduction of a die-to-database verification tool for the entire printed geometry of a die: geometry verification system NGR2100 for DFM

Tadashi Kitamura, Kazufumi Kubota, Toshiaki Hasebe, Futoshi Sakai, Shinichi Nakazawa, Neeti Vohra, Masahiro Yamamoto, Masahiro Inoue

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.620389

KEYWORDS: Computer aided design, Defect detection, Lithography, Semiconducting wafers, Edge detection, Design for manufacturing, Optical proximity correction, Critical dimension metrology, Photomasks, Inspection

Read Abstract +

Proceedings Article | 5 May 2005 Paper

Paper

Introduction of a die-to-database verification tool for the entire printed geometry of a die: geometry verification system NGR2100 for DFM

Tadashi Kitamura, Kazufumi Kubota, Toshiaki Hasebe, Futoshi Sakai, Shinichi Nakazawa, Neeti Vohra, Masahiro Yamamoto, Masahiro Inoue

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.599467

KEYWORDS: Computer aided design, Defect detection, Lithography, Optical proximity correction, Edge detection, Design for manufacturing, Semiconducting wafers, Photomasks, Inspection, Critical dimension metrology

Read Abstract +

Showing 5 of 18 publications

SIGN IN TO:

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Advertisement

Advertisement