Dr. Mauro Vasconi Profile

Dr. Mauro Vasconi

Metrology and Support Manager at Numonyx Agrate

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Publications (9)

Proceedings Article | 23 March 2009 Paper

Overlay metrology for double patterning processes

Philippe Leray, Shaunee Cheng, David Laidler, Daniel Kandel, Mike Adel, Berta Dinu, Marco Polli, Mauro Vasconi, Bartlomiej Salski

Proceedings Volume 7272, 72720G (2009) https://doi.org/10.1117/12.814182

KEYWORDS: Overlay metrology, Double patterning technology, Semiconducting wafers, Diffraction, Scanners, Calibration, Metrology, Diffraction gratings, Spectroscopy, Polarizers

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The double patterning (DPT) process is foreseen by the industry to be the main solution for the 32 nm technology node and even beyond. Meanwhile process compatibility has to be maintained and the performance of overlay metrology has to improve. To achieve this for Image Based Overlay (IBO), usually the optics of overlay tools are improved. It was also demonstrated that these requirements are achievable with a Diffraction Based Overlay (DBO) technique named SCOL^TM [1]. In addition, we believe that overlay measurements with respect to a reference grid are required to achieve the required overlay control [2]. This induces at least a three-fold increase in the number of measurements (2 for double patterned layers to the reference grid and 1 between the double patterned layers). The requirements of process compatibility, enhanced performance and large number of measurements make the choice of overlay metrology for DPT very challenging. In this work we use different flavors of the standard overlay metrology technique (IBO) as well as the new technique (SCOL) to address these three requirements. The compatibility of the corresponding overlay targets with double patterning processes (Litho-Etch-Litho-Etch (LELE); Litho-Freeze-Litho-Etch (LFLE), Spacer defined) is tested. The process impact on different target types is discussed (CD bias LELE, Contrast for LFLE). We compare the standard imaging overlay metrology with non-standard imaging techniques dedicated to double patterning processes (multilayer imaging targets allowing one overlay target instead of three, very small imaging targets). In addition to standard designs already discussed [1], we investigate SCOL target designs specific to double patterning processes. The feedback to the scanner is determined using the different techniques. The final overlay results obtained are compared accordingly. We conclude with the pros and cons of each technique and suggest the optimal metrology strategy for overlay control in double patterning processes.

Proceedings Article | 22 March 2008 Paper

Diffraction based overlay metrology: accuracy and performance on front end stack

Philippe Leray, Shaunee Cheng, Daniel Kandel, Michael Adel, Anat Marchelli, Irina Vakshtein, Mauro Vasconi, Bartlomiej Salski

Proceedings Volume 6922, 69220O (2008) https://doi.org/10.1117/12.772516

KEYWORDS: Overlay metrology, Scatterometry, Semiconducting wafers, Diffraction, Chemical mechanical planarization, Silicon, Etching, Metrology, Scanners, Detection and tracking algorithms

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Proceedings Article | 18 June 2007 Paper

Differential signal scatterometry overlay metrology: an accuracy investigation

Daniel Kandel, Mike Adel, Berta Dinu, Boris Golovanevsky, Pavel Izikson, Vladimir Levinski, Irina Vakshtein, Philippe Leray, Mauro Vasconi, Bartlomiej Salski

Proceedings Volume 6616, 66160H (2007) https://doi.org/10.1117/12.725929

KEYWORDS: Overlay metrology, Scatterometry, Semiconducting wafers, Detection and tracking algorithms, Computer simulations, Silicon, Standards development, Electromagnetism, Metrology, Algorithms

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Proceedings Article | 24 March 2006 Paper

In-chip optical CD measurements for non-volatile memory devices

Mauro Vasconi, Stephanie Kremer, M. Polli, Ermes Severgnini, Silvia Trovati

Proceedings Volume 6152, 61520D (2006) https://doi.org/10.1117/12.650997

KEYWORDS: Single crystal X-ray diffraction, Critical dimension metrology, Scatterometry, Silicon, Semiconducting wafers, Optical design, Reticles, Scanners, Optical testing, Etching

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Proceedings Article | 15 March 2006 Paper

Statistical shape analysis applied to microlithography

Alessandra Micheletti, Ermes Severgnini, Filippo Terragni, Mauro Vasconi

Proceedings Volume 6155, 61550J (2006) https://doi.org/10.1117/12.653037

KEYWORDS: Shape analysis, Semiconducting wafers, Optical lithography, Statistical analysis, Process control, Scanning electron microscopy, Electronic components, Edge detection, Control systems, Lithography

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Proceedings Article | 10 May 2005 Paper

Evaluation of Hitachi CAD to CD-SEM metrology package for OPC model tuning and product devices OPC verification

Pietro Cantu, Gianfranco Capetti, Chiara Catarisano, Fabrizio D'Angelo, Elena Evangelista, Ermes Severgnini, Silvia Trovati, Mauro Vasconi, Takumichi Sutani, Stephan Wahl, Robert Steffen

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.601909

KEYWORDS: Computer aided design, Scanning electron microscopy, Optical proximity correction, Semiconducting wafers, Image acquisition, Metrology, Critical dimension metrology, Instrument modeling, Detection and tracking algorithms, Visualization

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Optical proximity corrections are widely used in semiconductor industry to compensate non-linear effects occurring when printing features smaller than exposure wavelength. Most advanced OPC software packages simulate optical behavior starting from a physical description of illumination and projection optics, while the characterization of resist development and etch loading effects is still performed empirically, with different approaches that, generally, require the collection of a huge amount of experimental data. Due to the wide variety of target patterns, which makes conventional CD-SEM recipe creation impossible, critical dimension (CD) measurements are usually performed manually, requiring long time and, despite the attention paid while measuring, with poor guarantee of repeatability. The introduction of 193nm resists, much more sensitive to SEM e-beam exposure if compared to 248nm materials, required increased attention to be paid on both focusing and measuring phases in order to obtain reliable results. As well as OPC model tuning, the verification of correction effectiveness on product devices is performed almost in the same way leading to the same kind of issues. In order to overcome most of these problems ST is evaluating a new CD metrology package from Hitachi High Technologies; this tool allows fully automatic CD measurements starting from GDS II coordinate input. The exact recognition of measurement locations is obtained through an algorithm, based on the superposition of the drawn GDS II layout to the SEM wafer images, which allows achieving high positioning accuracy. The introduction of the tool significantly reduces measuring time down to the range of normal automated CD measurement times, while guarantying improved repeatability and optimized conditions even with 193nm resists due to the possibility of defining different structures for addressing and focusing before the measurement. This new system opens new perspectives in OPC modeling giving the opportunity of a more accurate model tuning, required by 65 nm technology node, and enables an extensive product devices OPC verification presently impossible due to time and procedure issues.

Proceedings Article | 2 June 2003 Paper

First review of a suitable metrology framework for the 65-nm technology node

Ermes Severgnini, Mauro Vasconi, David Herisson, Philippe Thony

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.482645

KEYWORDS: Metrology, Line edge roughness, Scatterometry, Scanning electron microscopy, Semiconducting wafers, Reticles, Silicon, Coating, Critical dimension metrology, Edge roughness

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Proceedings Article | 22 August 2001 Paper

193-nm metrology: facing severe e-beam/resist interaction phenomena

Mauro Vasconi, Maddalena Bollin, Gina Cotti, Laurent Pain, Vincent Tirard

Proceedings Volume 4344, (2001) https://doi.org/10.1117/12.436791

KEYWORDS: Critical dimension metrology, Scanning electron microscopy, Semiconducting wafers, Photoresist materials, Metrology, Electron beams, Target detection, Photoresist processing, Silicon, Ultraviolet radiation

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Proceedings Article | 22 May 1995 Paper

Near and sub-half-micrometer geometry SEM metrology requirements for good process control

Christopher Cork, Paolo Canestrari, Paolo De Natale, Mauro Vasconi

Proceedings Volume 2439, (1995) https://doi.org/10.1117/12.209238

KEYWORDS: Process control, Metrology, Scanning electron microscopy, Etching, Cadmium, Visibility, Lithography, Metals, Semiconducting wafers, Oxides

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Showing 5 of 9 publications

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