We describe a low-cost, low-power wireless sensor network we are developing for high time-resolution (ns-scale)
characterization of particle showers produced by ultra-high-energy (UHE) cosmic rays, to infer shower direction at sites
where hard-wired data connections may be inconvenient to install. The front-end particle detector is a scintillator block
monitored by a photomultiplier tube (PMT). We keep the sensor nodes synchronized to within 1 ns using periodic highintensity
optical pulses from a light-emitting-diode (LED) overdriven at very high current (~30 A) in short (4 ns) bursts.
With minimal optics, this signal is resolvable under free-space transmission in ambient light conditions at multi-meter
distances using a high-speed avalanche photodiode (APD) receiver at each node. PMT pulse waveforms are digitized
relative to this precise time reference on a Field Programmable Gate Array (FPGA) using a Time-over-Threshold
(ToT)/Time-to-Digital Converter (TDC) digitizer developed at BNL. A central server receives timestamped, digitized
PMT pulse waveforms from the sensor nodes via Wi-Fi and performs real-time data visualization & analysis. Total cost
per sensor node is a few thousand dollars, with total power consumption per sensor node under 1 Watt, suitable for, e.g.,
solar-powered installations at remote field locations.
Conventional vector-based simulators for quantum computers are quite limited in the size of the quantum circuits they
can handle, due to the worst-case exponential growth of even sparse representations of the full quantum state vector as a
function of the number of quantum operations applied. However, this exponential-space requirement can be avoided by
using general space-time tradeoffs long known to complexity theorists, which can be appropriately optimized for this
particular problem in a way that also illustrates some interesting reformulations of quantum mechanics. In this paper, we
describe the design and empirical space/time complexity measurements of a working software prototype of a quantum
computer simulator that avoids excessive space requirements. Due to its space-efficiency, this design is well-suited to
embedding in single-chip environments, permitting especially fast execution that avoids access latencies to main
memory. We plan to prototype our design on a standard FPGA development board.
Fully-adiabatic (thermodynamically reversible) logic is one of the few promising approaches to low-power logic design. To maximize the system power-performance of an adiabatic circuit requires an ultra low-loss on-chip clock source, which can generate an output signal with a quasi-trapezoidal (flat-topped) voltage waveform. In this paper, we propose to use high-Q MEMS resonators to generate the custom waveform. The big challenge in the MEMS resonator design is that a non-sinusoidal (quasi-trapezoidal) waveform needs to be generated even though the resonator oscillates sinusoidally. Our solution is to customize the shape of the sensing comb fingers of the resonator, with the result that the sensing capacitance varies quasi-trapezoidally. The effective quality factor and the area-efficiency of the microstructure have been optimized so as to minimize the whole system’s power dissipation and cost at a given frequency. A resonator design with a 100 kHz resonant frequency based on a standard TSMC 0.35μm CMOS process has been fabricated. The resonator has an area of 300 μm by 160 μm with a thickness of 30 μm. Three-dimensional field simulation shows that the resonator generates a quasi-trapezoidal waveform when it operates at its resonance. An on-chip buffer is also designed for monitoring the waveform generated by the MEMS resonator. The post-CMOS fabrication process is compatible with standard CMOS processes. Thus the custom clock generator can be integrated with logic circuits on the same CMOS chip. The size of the MEMS resonator can be further reduced by design optimization and advances in micro/nano-fabrication technology.
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