Nano-imprint lithography (NIL) tool for semiconductor manufacturing employs die-by-die alignment system. For semiconductor device manufacturing, precise alignment of template mark and wafer mark that is composed of various film stacks, is required to achieve good overlay accuracy. We have studied the relation of wafer stack structure and NIL alignment accuracy. Using FPA-1200NZ2C (Canon Corp.), we have evaluated imprint performance on the wafers with different stacks. In this paper, we describe (i) alignment performance of the state-of-the art NIL tool, (ii) simulation of NIL alignment mark signal, and (iii) capability of NIL alignment system for various wafer stack structure.
Ultraviolet nanoimprint lithography (NIL) is a simple contact process that is attractive and promising process for high pattern fidelity, without blurring effect due to light scattering or acid diffusion in the resist. Specifically, complicated 3D patterns, fine 2D patterns, and fine 1D patterns can be formed in fewer process steps compared to those for optical lithography. On the other hand, there are fewer adjustment knobs for process tuning in NIL; therefore, it is necessary to introduce design restrictions customized for NIL to improve the process margin. Since pattern transfer is performed through filling of a resist having a finite volume, a design constraint considering filling property is required to reduce defect density and improve throughput. In this study, two types of design constraints are examined to address the NIL process margin problem. One is a NIL alignment mark design that satisfies both signal strength and filling characteristics. The other is a combination of the pattern coverage rule with wafer topography that achieves good filling characteristics under various substrate unevenness conditions. Experiment results were interpolated with NIL process simulations and common areas under various conditions were extracted to identify the design rules for achieving large process margins. By using a design flow that considers these rules, we believe that high volume manufacturing (HVM) yields can be increased considerably by reducing yield issues and reducing redesign loops.
To improve the productivity of nanoimprint lithography (NIL) in semiconductor manufacturing, we have developed spin-coating and flash imprint lithography (SC-FIL). Using a newly developed SC-FIL resist, we imprinted a 300-mm-wide whole wafer including partial fields. The cross-sectional image showed a well-shaped half-pitch dense line with a width of 26 nm. The mix-and-match overlay accuracy (3σ) was 3.9 nm in the X direction and 3.4 nm in the Y direction. Assuming Washburn’s model of capillary flow, we identified the unique defect-generation mechanism in SC-FIL and hence optimized the SC-FIL process for high throughput and low defect density. After optimizing the NIL, the multimodule NZ2C system with four imprint heads is expected to achieve a throughput of 124 wafers per hour and a defectivity of only 0.005 defects per cm2.
Nanoimprint lithography (NIL) has been received attention as an alternative lithographic technology, which can fabricate fine patterns of semiconductor devices at low cost, by transferring fine pattern of a template on to a resist layer by physical contact of template and resist followed by the resist curing. For more than a decade, we have been developing Jet and Flash Imprint Lithography (J-FIL) technology and challenging critical issues such as defect density, overlay, and throughput.
J-FIL is an efficient process for transferring template pattern having large variations in pattern density. However, it has the intrinsic limitation of lower throughput due to resist dispensing time prior to imprinting of every single field on the wafer and the spreading process of resist drops, slow diffusion of bubble trapped at the resist drop-boundaries. To eliminate the above mentioned steps and improve throughput, we have developed a spin coating NIL (SCN) process in which a uniform resist layer is spin coated on the entire wafer.
Identification of defect generation mechanism assuming Washburn’s model of capillary flow, has led us to optimize SCN process and thus achieving a higher throughput with lower defect density as compared to that of the J-FIL process. We will show the defect density and throughput performance of SCN process, and the possibility of introducing SCN in device production.
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