Ms. Nazeen Jeewakhan Profile

Nazeen Jeewakhan

Process Development Engineer at Western Digital Corp

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Publications (3)

Proceedings Article | 20 October 2006 Paper

Application of Dosemapper for 65-nm gate CD control: strategies and results

Nazneen Jeewakhan, Nader Shamma, Sang-Jun Choi, Roque Alvarez, D. Son, Makoto Nakamura, Vinny Pici, Jim Schreiber, Wei-shun Tzeng, Sean Ang, Daniel Park

Proceedings Volume 6349, 63490G (2006) https://doi.org/10.1117/12.692938

KEYWORDS: Etching, Critical dimension metrology, Semiconducting wafers, Charge-coupled devices, Lithography, Tolerancing, Reticles, Manufacturing, Neodymium, Photomasks

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Proceedings Article | 17 December 2003 Paper

DUV mask writer for BEOL 90-nm technology layers

Dongsung Hong, Prakash Krishnan, Dianna Coburn, Nazneen Jeewakhan, Shengqi Xie, Joshua Broussard, Bradley Ferguson, Kent Green, Peter Buck, Curt Jackson, Larry Martinez

Proceedings Volume 5256, (2003) https://doi.org/10.1117/12.518051

KEYWORDS: Photomasks, Deep ultraviolet, Semiconducting wafers, Metals, Vestigial sideband modulation, Reticles, Optical proximity correction, Back end of line, Critical dimension metrology, Cadmium

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Proceedings Article | 2 June 2003 Paper

Faster qualification of 193-nm resists for 100-nm development using photo cell monitoring

Chris Jones, Chidam Kallingal, Mary Zawadzki, Nazneen Jeewakhan, Nazila Kaviani, Prakash Krishnan, Arthur Klaum, Joel Van Ess

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.504591

KEYWORDS: Photoresist materials, Semiconducting wafers, Optical lithography, Inspection, Etching, Critical dimension metrology, Scanning electron microscopy, Wafer testing, Semiconductors, Photoresist processing

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The development of 100-nm design rule technologies is currently taking place in many R&D facilities across the world. For some critical alyers, the transition to 193-nm resist technology has been required to meet this leading edge design rule. As with previous technology node transitions, the materials and processes available are undergoing changes and improvements as vendors encounter and solve problems. The initial implementation of the 193-nm resits process did not meet the photolithography requirements of some IC manufacturers due to very high Post Exposure Bake temperature sensitivity and consequently high wafer to wafer CD variation. The photoresist vendors have been working to improve the performance of the 193-nm resists to meet their customer's requirements. Characterization of these new resists needs to be carried out prior to implementation in the R&D line. Initial results on the second-generation resists evaluated at Cypress Semicondcutor showed better CD control compared to the aelrier resist with comparable Depth of Focus (DOF), Exposure Latitute, Etch Resistance, etc. In addition to the standard lithography parameters, resist characterization needs to include defect density studies. It was found that the new resists process with the best CD control, resulted in the introduction of orders of magnitude higher yield limiting defects at Gate, Contact adn Local Interconnect. The defect data were shared with the resists vendor and within days of the discovery the resist vendor was able to pinpoint the source of the problem. The fix was confirmed and the new resists were successfully released to production. By including defect monitoring into the resist qualification process, Cypress Semiconductor was able to 1) drive correction actions earlier resulting in faster ramp and 2) eliminate potential yield loss. We will discuss in this paper how to apply the Micro Photo Cell Monitoring methodology for defect monitoring in the photolithogprhay module and the qualification of 193nm resist processes.

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