OPC models have become critical in the manufacturing of integrated circuits (ICs) by allowing correction of complex designs, as we approach the physical limits of scaling in IC chip design. The accuracy of these models depends upon the ability of the calibration set to sufficiently cover the design space, and be manageable enough to address metrology constraints. We show that the proposed method provides results of at least similar quality, in some cases superior quality compared to both the traditional method and sample plan sets of higher size. The main advantage of our method over the existing ones is that it generates a calibration set much faster, considering a large initial set and even more importantly, by automatically selecting its minimum optimal size.
It is desired to reduce the time required to produce metrology data for calibration of Optical Proximity Correction (OPC) models and also maintain or improve the quality of the data collected with regard to how well that data represents the types of patterns that occur in real circuit designs. Previous work based on clustering in geometry and/or image parameter space has shown some benefit over strictly manual or intuitive selection, but leads to arbitrary pattern exclusion or selection which may not be the best representation of the product. Forming the pattern selection as an optimization problem, which co-optimizes a number of objective functions reflecting modelers’ insight and expertise, has shown to produce models with equivalent quality to the traditional plan of record (POR) set but in a less time.
Process models have been in use for performing proximity corrections to designs for placement on lithography masks for
a number of years. In order for these models to be used they must provide an adequate representation of the process
while also allowing the corrections themselves to be performed in a reasonable computational time. In what is becoming
standard Optical Proximity Correction (OPC), the models used have a largely physical optical model combined with a
largely empirical resist model. Normally, wafer data is collected and fit to a model form that is found to be suitable
through experience. Certain process variables are considered carefully in the calibration process-such as exposure dose
and defocus - while other variables-such film thickness and optical parameter variations are often not considered. As
the semiconductor industry continues to march toward smaller and smaller dimensions-with smaller tolerance to errorwe
must consider the importance of those process variations. In the present work we describe the results of experiments
performed in simulations to examine the importance of many of those process variables which are often regarded as
fixed. We show examples of the relative importance of the different variables.
Electrical validation of through process optical proximity correction verification limits in 32-nm process technology is presented. Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence of each process conditions. The design of electrical layouts is extended to subdesign rules to force failure and derive better correlation between electrical and simulated outputs. Some of these subdesign rule designs amplify the failures induced by an exposure tool, such as optical aberrations. Observations in this regard are reported. Sensitivity with respect to dimensions, orientations, and wafer distribution are discussed in detail.
Electrical validation of through process OPC verification limits in 32nm process technology is presented in this paper.
Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence
of each process conditions. The design of electrical layouts is extended to sub ground rules to force failure and derive
better correlation between electrical and simulated outputs. Some of these sub ground rule designs amplify the failures
induced by exposure tool, such as optical aberrations. Observations in this regard will be reported in the paper.
Sensitivity with respect to dimensions, orientations and wafer distribution will be discussed in detail.
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