In this work, we quantify the non-uniformity in the spin current density generated by spin-orbit torque (SOT) at the nanoscale and its impact on the switching of SOT magnetic random-access memories (MRAMs). In recent years, SOTMRAMs have emerged as promising non-volatile candidates for last-level (L3/L4) cache due to their high endurance, sufficiently low read/write latency, long retention times, and scalability. In these devices, a conduction current is passed through the non-magnetic (NM) layer, which generates a spin current flowing towards the ferromagnetic (FM) layer due to the Spin Hall Effect (SHE). Using conventional drift-diffusion models, which consider the electric current distribution to be uniform within the FM and NM layers, can lead to erroneous results in the case of nanoscale devices. In this paper, we use the spin current distribution calculated based on finite element simulations and drift-diffusion equations in micromagnetic simulation. We demonstrate that spin current density can be significantly lower at the two edges of the magnet compared to the middle and this non-uniformity can affect the magnet switching dynamics. We investigate the impact of this non-uniformity for both perpendicular magnetic anisotropy (PMA) and in-plane magnetic anisotropy (IMA) based magnetic tunnel junctions (MTJs). Our results show that when resistive NM layers are used, the impact of nonuniform spin current density on write times is more significant for larger FMs. In addition, the variation in write times is more significant in the case of PMA FM than IMA FM.
Spin-orbit torque (SOT) devices are being pursued for various memory and in-memory compute applications. At nanoscale dimensions, electric current flowing through the SOT channel can be non-uniform due to incomplete current redistribution. Such effects were ignored in the prior modeling works. We present a comprehensive modeling framework for SOT devices that capture the effects of incomplete current redistribution along with interface spin-mixing, and non-uniform resistivity. Our transfer matrix-based formalism along with finite element simulations can account for any local variation in resistivity and spin diffusion length along with accounting for various spin-scattering mechanisms. In addition, we quantify the optimal SOT layer thickness to minimize the write energy in terms of its resistivity and spin diffusion length. To improve the bit density of SOT magnetic random-access memory (MRAM), we explore area saving schemes based on sharing SOT channel among multiple magnetic tunnel junctions (MTJs) with the help of voltage-controlled magnetic anisotropy (VCMA) effect and spin-transfer torque (STT). Using micromagnetic simulations, we study various tradeoffs among write time, current, error rate, and the number of MTJs. Our results show that the number of MTJs on the shared SOT channel is limited by the voltage drop over the SOT channel and write error rate, and having more than 4 MTJs on a SOT channel poses major challenges in terms of reliability.
A diverse set of novel materials, physical phenomena, logic/memory devices, and circuit/system options/concepts are being pursued globally to design and develop the next generations of information storage and processing platforms. Many of these potential options are vastly different compared to their conventional counterparts and cannot be used as drop-in replacements. This research should therefore include several levels of abstraction, and must take a holistic approach to truly leverage the benefits offered by the promising options. Among the emerging materials and devices, magnetic and multiferroic devices are of particular interest thanks to their non-volatility, density, energy efficiency and durability. This paper presents a co-design framework for magnetic materials, devices, and memory arrays based on a hierarchy of physical models. Two major categories of devices are considered: spin-orbit-torque (SOT) and magnetoelectric (ME) random access memories. Circuit compatible experimentally validated/calibrated physical models for such devices is presented and used to optimize material and device parameters to minimize energy/delay for read and write operations for various target error rates. Finally, novel SOT and ME based cell designs for ternary content-addressable memories (TCAM) are presented and their potential performance is quantified against their SRAM and FeFET based designs using a comprehensive modeling and benchmarking framework.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.