We introduce a novel method for low substrate temperature carbon nanotube (CNT) deposition utilizing photo-chemical
vapor deposition (PCVD). Aluminum and nickel catalyst layers are deposited on thermally oxidized silicon substrates for
CNT growth. The catalyst layers of varying thicknesses are deposited by electron beam evaporation. Different catalyst
annealing temperatures and pressures are investigated. The CNT deposition is carried out immediately following the
annealing process. The presence of light source during CNT deposition assists in fragmentation of the CCl4 precursor
molecules used, thereby permitting a lower substrate temperature during growth. We have successfully deposited CNTs
at substrate temperatures as low as 400 °C by this technique.
As the power consumption of modern electronics and wireless circuits decreases to a few hundred microwatts, it
becomes possible to power these electronic devices by using ambient energy harvested from the environment.
Mechanical vibration is among the more pervasive ambient available energy forms. Recent works in vibration-to-electrical
energy harvesters have been centered on high frequency vibration applications. Although high-frequency
mechanical vibrations are more energy rich, for some situations the local ambient environmental vibrations tend to occur
at lower-frequencies. For example, the highway vibration frequencies are mainly between 10 ~ 20 Hz. This paper
discusses the development of a miniature vibration-to-electrical energy harvester based on electromagnetic methods
using MEMS technology, targeted on the low vibration frequency regime in the 15 ~ 20 Hz range for potential use in
highway structural health monitoring (HSHM) purposes or in other applications. Innovative design considerations need
to be addressed to achieve this goal in a miniature package. For example, a highly pliant material and a heavy seismic
mass are needed. In our design, SU-8 is chosen as a part of the composite material for the cantilever beam, micro-coil,
and seismic mass fabrication. The mechanical characteristics of the energy harvester are simulated. The power
generation capability of the designed energy harvester is calculated.
This work investigates both DC and pulse electroplating techniques for nickel. A nickel sulfamate electrolyte is utilized for nickel deposition over Cu/Ti coated silicon substrates. Stress levels and grain morphology are investigated and analyzed for the electroplated nickel deposit. A comparison is also made between the results obtained from DC and from long and short duration pulse electroplating techniques. Both compressive and tensile built-in stresses are observed in both DC and long duration pulse plated nickel while only compressive stresses are observed in short duration pulse plated nickel.
A post-CMOS process for chip-level monolithic integration has been developed. A metal probe array for recording neural signals is utilized as a test vehicle to realize the integration process. This probe array is fabricated on a 2 mm x 2 mm chip containing eight ultra-low power CMOS operational amplifiers. A LIGA-like process is employed utilizing UV lithography on SU-8 photoresist and pulse electroplating technique. Pulse plating significantly reduces stress in the deposited material. The post-CMOS fabrication process is utilized to fabricate 70 μm high probes having different aspect-ratios that are monolithically integrated on the CMOS chip.
The charge pump CMOS circuit designs are presented for bio-medical applications wherein the clock voltage is boosted internally. Four and six-stage charge pumps are implemented in 1.5 μm n-well CMOS process. The charge pump circuits can be operated in 1.2 V - 3 V power supply voltage range. Outputs of 12.5 V and 17.8 V are measured from four and six-stage charge pumps, respectively with a 3 V power supply. The charge pump circuits can also be used to generate clock voltage higher than the input clock voltage. In the present design, the clock voltages, 8 V and 11 V have been generated from four-stage and six-stage charge pumps, respectively which are nearly 2.5 and 4 times the input clock voltage of 3 V. The technique of boosting the clock internally has been applied in implementation of a bio-implantable battery powered electrical stimulation chip.
In this work, a remote power delivery system to charge rechargeable batteries that power a Bio-implanted Electrical Stimulation System (BESS) is first described. A loosely coupled inductive transmitter and receiver system has been used to power a bio-implanted gastric pacer. The receiver coil, rechargeable batteries, battery charging chip and the chip containing stimulation circuitry form a hybrid integrated microsystem. A design methodology for this Remote Power Delivery System (RPDS) is proposed. The BESS chip is also designed for electrical stimulation. It is a special IC chip which takes power from the rechargeable batteries and provides output pulses of 9.9 V amplitude at a frequency of 103 Hz and a duty cycle of 5%. The BESS chip contains a battery switching circuit and a pulse conditioning circuit which first provides pulses of 3 V amplitude. It also has an internal charge pump and a pulse booster circuit to boost the pulse amplitude to 9.9 V. Hybrid packaging is considered for integrating the implantable electrical stimulation circuitry and the remote power delivery system. Screen printed interconnects are used to integrate the BESS chip, the battery charging chip, discrete components and the receiver circuit of the RPDS.
KEYWORDS: Analog electronics, Multiplexers, Field effect transistors, Transistors, Switches, Device simulation, Signal processing, Sensors, CMOS technology, Signal detection
A CMOS analog multiplexer circuit has been designed for operation at 0.8 V. The circuit consists of transmission gates as switches and an inverter. MOSFETs in the design of multiplexer use the dynamic body bias method. The forward body bias is limited to no more than 0.4 V to avoid CMOS latch-up. The reverse body bias is limited to 0.4 V and allows the MOSFET to turn-off fully and suppresses the sub-threshold leakage. The improved dynamic threshold MOSFET (DTMOS) inverter is engaged to achieve low voltage operation. The CMOS multiplexer chip was designed in standard 1.5 μm n-well CMOS technology and simulated using SPICE. Excellent agreement was obtained between the simulated output waveform and corresponding experimentally measured behavior. The power dissipation is close to 70 nW and signal-to-leakage ratio is 120 dB. The proposed low voltage, ultra-low power analog multiplexer would find application for on-chip neural microprobes and other applications.
A microprobe array for recording neural signals has been designed and fabricated for future monolithic integration with an ultra-low power CMOS operational amplifier circuit on a 2 mm × 2 mm chip. A LIGA-like process is employed utilizing UV lithography and electrodeposition techniques. Probes are fabricated on silicon substrate. The fabrication process is compatible with monolithic integration with CMOS signal processing circuitry. The probes are 210 um high and have an aspect ratio 3:1. Comments are made on processing issues related to chip-level monolithic integration.
A new position sensor based on laterally movable gate FET (LMGFET) sensing element has been designed and fabricated. The position sensor is designed to operate in a differential mode, which increases device sensitivity and performance. The moving proof mass is supported on each end by a folded beam which is also employed as a spring to restrain motion. The simulated value of the folded beam spring constant designed in this work is 44.8 N/m. The LMGFET microstructure is fabricated by a four-mask LIGA-like post-IC process compatible with standard CMOS fabrication technology. p+ region is ion-implanted under the moving structure as a ground plane and also to decrease leakage currents. Plasma ashing is employed to avoid stiction. The design of the sensor along with fabrication steps is described. Preliminary results on the electrical behavior of the fabricated LMGFET are given.
Design, simulation, and fabrication of an integrated microaccelerometer, which is one of several applications of a novel device called Laterally Movable Gate FET (LMGFET) are presented. A LIGA-like post-IC fabrication method compatible with monolithic integration of electronic circuits in standard CMOS technology is utilized to fabricate the accelerometers. External acceleration results in motion of LMGFET differential gates, which cause the drain currents in the FETs to change linearly with position and hence motion. Two types of designs are utilized as restraining springs, which are rigidly anchored to the substrate. The gate motion is first simulated by FEM to analyze its mechanical response. The simulation predicts resonance frequencies of the structures to be 6.32 kHz and 4.66 kHz and gate mechanical motion sensitivity values of 6.23 and 11.47 nm/unit acceleration in g. The op-amp is designed, simulated using PSPICE and fabricated using a 1.5 μm standard CMOS process to amplify the sensor output signal. The simulated values for sensitivity of the two accelerometers are 0.23 mV/g and 0.42 mV/g for the folded beam and the serpentine structure, respectively for an amplifier gain of 45.4 (33.14 dB). The LMGFET microaccelerometers show promise for extremely high dynamic linear operating range.
A CMOS test chip has been designed and fabricated which can monolithically integrate ultra low-power operational amplifiers with neural microprobes through post-IC processing. Neural microprobes of varying widths (70 μm, 60 μm, 50 μm, and 40 μm) are designed with varying center-to-center spacing (195 μm, 175 μm, 165 μm, 155 μm, 145 μm, and 125 μm) on a test chip for integration. Neural microprobes are first fabricated on a separate Si substrate to develop a fabrication process for post-IC processing for integration. The amplifier is designed in standard 1.5 μm CMOS process for operation at ∓ 0.4 V. Low power performance is realized by combining forward biased source-substrate junction MOSFETs with a novel low-voltage level-shift current mirror. The designed amplifier gives a gain of 7000 (77 dB) and a 3-dB bandwidth of 30 kHz. The amplifier output has a positive offset of only 20 μV and power dissipation of only 40 μW.
KEYWORDS: Amplifiers, Field effect transistors, Resistance, Mirrors, Signal to noise ratio, Power supplies, Device simulation, Transistors, Standards development, Solids
Noise due to back-gate forward bias between substrate and source of a MOSFET is analyzed and simulated. Noise level is compared between two CMOS circuits with and without back-gate forward bias. It is found that the output noise introduced by the back-gate forward bias method is only a few nV/square root (Hz), which only slightly increases the device noise. A CMOS op-amp is designed utilizing back-gate forward bias technique utilizing a level shift current mirror for operation at ultra low-power in μW range. The designed amplifier dissipates power of 40 uW and operates at ± 0.4 V to achieve a gain of 77 dB. The noise in ultra low-power op-amp is also investigated. The total output noise density is about 30 μV/square root (Hz) in the ultra-low power op-amp design, which is lower than 65 μV/square root (Hz) of standard op-amp. The signal to noise ratio of the ultra low-power op-amp is 44 dB.
Circuit design for a novel scheme for converting a multiple- valued output voltage forma sensor into a binary-coded output for signal processing is described here. Floating gate MOSFETs and floating gate potential diagrams have been used to design a readout integrated circuit in a standard 1.5 micrometers digital CMOS VLSI technology. The physical design is simulated and tested with SPICE using MOSIS BSIM3 MOS model parameters. Initial results on fabricated devices for the conversion of quaternary input into binary output have shown agreement with the corresponding simulated values. The method is simple and compatible with current CMOS processes. The circuit can be integrated with output of a sensor fabricated in MEMS-CMOS technology.
In our previous work, we had reported initial results on electrical behavior of a novel device called Laterally Movable Gate Field Effect Transistor or LMGFET. In this device, the gate of a FET moves parallel to the substrate surface, which causes the drain current to change linearly to gate motion. In this paper, we describe a potential application of this device as a resonant gate structure. A folded beam structure is utilized as a restraining spring in order to make spring more flexible in the direction of motion compared to the other two orthogonal directions. A high aspect ratio structure is utilized to decrease motion in the direction vertical to the substrate. The resonance frequency can be changed with device geometry resulting in an array of devices with different resonance frequencies on a chip. Five different resonant gate structures are designed with resonance frequencies lying in the audio frequency range. The structures are simulated by analytical and numerical methods. Damping effects are considered in the simulations resulting in quality factor Q values in the range of 500 to 1440 under atmospheric conditions for the designed structures.
Operation of a new device structure called Laterally Movable Gate Field Effect Transistor (LMGFET) is reported here. The device drain current changes linearly with lateral gate motion. A prototype test device was designed and fabricated in our laboratory. A novel three-mask LIGA compatible process was used for device fabrication. A comb drive structure was used to drive the movable gate. On the unoptimized test device, static sensitivity to gate position of 6.4 A/m was observed in saturation with zero gate to source voltage. For the ac drive voltage on the comb drive, a sensitivity of 3.2 nA change in drain current per volt of ac drive voltage were observed at a dc bias of 38 V. Significant improvement in device performance are possible with changes in device design. This, to our knowledge, is the first report on the operation of a LMGFET with a driven gate.
A novel device to directly integrate mechanical motion with electronics on a chip for system integration is designed and fabricated. The device is a laterally movable gate field effect transistor. Here the gate moves parallel to the substrate surface rather than perpendicular to its as in the moving gate transistors reported earlier. Lateral motion results in linear response of device drain current with gate motion. It also makes large motion possible. The device has a variety of applications in smart sensors, actuators and integrated smart systems. A simple fabrication process is developed that is compatible with fabrication of high-aspect ratio structures. The latter give distinct performance improvement. The basic principles of operation of the LMGFET is demonstrate din initial measurements. This, to our knowledge, is the first report on the operation of such a device.
Processing technique for fabrication of high-aspect ratio structures in PZT is developed in this work using deep X-ray exposures at the CAMD synchrotron storage ring. Arrays of posts were successfully fabricated in PMMA mold as thick as 2700 micrometers and with aspect ratio as high as 15. This LIGA- like technique allows fabrication of structures of shapes and sizes not possible with standard techniques using bulk PZT material or by the existing thin film techniques for PZT deposition. The process shows promise for various applications including high resolution medical imaging and optical projection.
A digital readout design in CMOS technology is described for monolithic integration with microelectromechanical capacitive sensors using on-chip variable sense capacitor arrays with resolutions of 2.5 fF, 10 fF and 40 fF, respectively. The designed circuit produces a 4-bit digital readout proportional to the capacitive difference between the sense and the reference capacitors. The CMOS digital readout is compatible with +/- 1.5 V operation for low power consumption, uses a +1.5 V reference voltage with a switching speed of approximately 100 kHz. The digital readout design presented here is quite general and can be used in a wide variety of analog microsensors on the chip.
KEYWORDS: Analog electronics, Sensors, Amplifiers, Electronics, Digital electronics, CMOS sensors, CMOS technology, Signal detection, Signal processing, Microelectromechanical systems
A digital readout electronics scheme in CMOS technology is described for integration with microelectromechanical sensors on the same chip. The readout criteria is general in nature and can be employed with a variety of analog sensors. The presented scheme in CMOS technology is fully integrable with the multiple sensor outputs either in a chain or an array format and is capable of detecting low analog output signals from a few (mu) V to mV range. The CMOS circuit design is compatible with +/- 1.5 V operation for low power consumption.
A cost-effective process with short fabrication time for making x-ray masks for research and development purposes is described here for fabricating high-aspect ratio microelectromechanical structures using synchrotron based x- ray lithography. Microscope cover glass slides as membrane material is described. Slides with an initial thickness of 175 micrometers are etched to a thickness in the range of 10 - 25 micrometers using a diluted HF and buffered hydrofluoric acid solutions. The thinned slides are glued on supportive mask frames and sputtered with a chromium/silver sandwich layer which acts as a plating base layer for the deposition of the gold absorber. The judicial choice of glue and mask frame material are significant parameters in a successful fabrication process. Gold absorber structures are electroplated on the membrane. Calculations are done for contrast and dose ratio obtained in the photoresist after synchrotron radiation as a function of the mask design parameters. Exposure experiments are performed to prove the applicability of the fabricated x-ray mask.
Successful direct integration of a mechanical structure fabricated by LIGA on a Si chip containing CMOS circuitry has been achieved in this work. A 1D cantilever accelerometer is chosen as a vehicle to demonstrate this integration process. The capacitive sensor element employs one electrode formed in the Si substrate during the integrated circuit fabrication. The other electrode is fabricated using the LIGA technique with sacrificial layer etching. Details of the fabrication process to achieve this integration are given. Need for careful control of stress in the deposited layers and achieving appropriate contrast in the X-ray mask are delineated.
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