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In this work, we propose a novel adaptive slicing algorithm that balances accuracy and print time. The proposed, near-optimal, dynamic programming (DP) based algorithm for adaptive slicing minimizes the number of layers subject to a global volumetric error constraint. Our approach reduces slice count by up to 36% (52%) compared to a state of the art adaptive slicing (uniform slicing) method under the same volumetric error. The results were tested on Formlabsunder the same volumetric error. The results were tested on Formlabs Form1+ SLA-based printers. The print time was improved by up to 32% (53%) for a selection of objects.
This course explains how layout and circuit design interact with lithography choices. We especially focus on multi-patterning technologies such as LELE double patterning and SADP. We will explore role of design in lithography technology development as well as in lithographic process control. We will further discuss design enablement of multi-patterning technologies, especially in context of cell-based digital designs.
EUV lithography and DSA haven been accepted by the industry as most promising candidates for dimensional scaling enablement at N7 technology node and beyond. This tutorial explains how introduction of such lithography technologies going to impact layout and circuit design. Choices of lithography would impact physical design and have a significant impact at system level. This tutorial will focus on transition from 193i multi-patterning technologies to EUV lithography and DSA. Factors that would determine on the enablement of these technologies would be highlighted and possible solutions would be shared.
Sub-90nm CMOS technologies are giving rise to significant variation in physical parameters of VLSI designs which has adverse impact on their electrical behavior. Most manufacturing-oriented professionals are familiar with the variations in physical parameters. This course will provide attendees with knowledge of how these physical variations impact the circuit operations, i.e., their electrical behavior. The impact on timing as well as power will be discussed. We will describe relative impact of these variations on various circuit families as well as circuit design techniques to mitigate the impact of manufacturing variations. Due to the large mangnitude of these variations, it is clear that designing for worst case behavior leaves significant performance on the table. We will discuss how systematic variation can be exploited in the current static timing methodology if it is known. A statistical timing and design methodology will also be discussed that can help regain some of this performance. With an eye towards the future, we will also explore manufacturing aware design closure. The course will be illustrated with practical examples throughout.
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