In this paper, we propose a novel modular patterning technology to reduce the edge-placement errors (EPE) significantly by combining alternating-material self-aligned multiple patterning (altSAMP) and selective etching processes. It is assumed that gates and fins are fabricated by the same type of altSAMP process as mixing two different processing techniques will drive up the manufacturing costs. Process variability induced circuit performance degradation is shown to be a serious issue as FinFET devices are scaled down to sub-10nm. We analyze the dependence of FinFET-based SRAM circuit performance on supply voltage, fin-width and gate-length variations. Improved device control with narrower fins helps to increase the static noise margin (SNM) in all SRAM cell designs. Higher supply voltage is also beneficial to the SNM performance. Our simulation results show that 6-T SRAM circuit design does not meet the six-sigma yield requirement when the half pitch is scaled down to sub-7 nm. To reduce the SRAM circuit variability, we study an 8-T SRAM cell and show that it significantly improves the SRAM performance.
In this paper, we present a compact model to predict the pillar-edge-roughness (PER) effects on 3D vertical nanowire MOSFETs using the perturbation method. An analytic solution to 3D Poisson’s equation in the cylindrical coordinate with a perturbed boundary is obtained to describe the PER effects on the vertical channel potential. The induced variations of drain current, threshold voltage (Vth), and sub-threshold slope (SS) are calculated using the developed model. We also investigate the PER phase and frequency dependent behavior of the nanowire MOSFETs, and find that both phase and (angular) frequency of the PER function will significantly affect the device performance. Our model calculation results are compared with TCAD simulations and a good agreement between them is found. It is suggested that our metrology society needs to develop relevant measurement methodology to characterize the nanowire pillar-edge roughness at deep nanoscale.
In this paper, we develop statistical models to investigate SRAM yield performance and circuit variability in the presence of self-aligned multiple patterning (SAMP) process. It is assumed that SRAM fins are fabricated by a positivetone (spacer is line) self-aligned sextuple patterning (SASP) process which accommodates two types of spacers, while gates are fabricated by a more pitch-relaxed self-aligned quadruple patterning (SAQP) process which only allows one type of spacer. A number of possible inverter and SRAM structures are identified and the related circuit multi-modality is studied using the developed failure-probability and yield models. It is shown that SRAM circuit yield is significantly impacted by the multi-modality of fins’ spatial variations in a SRAM cell. The sensitivity of 6-transistor SRAM read/write failure probability to SASP process variations is calculated and the specific circuit type with the highest probability to fail in the reading/writing operation is identified. Our study suggests that the 6-transistor SRAM configuration may not be scalable to 7-nm half pitch and more robust SRAM circuit design needs to be researched.
In this paper, a generalized model to predict fin-width roughness (FWR) induced FinFET device variability is developed using the boundary perturbation method. An analytic solution to Poisson’s equation with a perturbed boundary is derived to describe the FWR effects on the sub-threshold electric potential and drain current. High model accuracy under various device operating conditions is demonstrated by a detailed comparison with TCAD simulations. The correlation among the threshold-voltage shift, dominant fin-roughness frequency, and phase difference (between two dominant fin-edge roughness functions) is identified. It is found that a periodic fluctuation of the threshold voltage can be induced by the phase difference, while more significant variations are observed at lower frequencies. Our study also shows that thinner gate oxide and wider fins will help to reduce the FWR effects.
The impacts of self-aligned triple patterning (SATP) and self-aligned quadruple patterning (SAQP) process variability on SRAM circuit performance are studied in this paper. Different types of SRAM circuit variability such as intra-cell and inter-cell variability are discussed. Spatially periodic variation patterns of a SRAM array fabricated with SATP process is identified, while spatial variation of SAQP based SRAM array is found to be less significant. Statistical TCAD simulations are carried out to examine the process variability induced fluctuation of SRAM circuit performance. It is found that SRAM static noise margin (SNM) shrinks with increased variations in line-width roughness and CD, especially when the technology node is scaled down. Despite the SATP/SAQP process variability and the related SNM reduction, our simulations show that the induced fluctuation of SRAM circuits is still manageable. It is also confirmed that circuit stability and manufacturing yield of SAQP based SRAM are better than SATP based SRAM.
A compact model is developed to study the fin-width roughness (FWR) induced device variability and its impacts on FinFET performance. The perturbation theory is applied to obtain the analytic solution to nonlinear Poisson’s equation by treating FWR as a small deviation/perturbation from the ideal (flat) fin boundary. High accuracy of this compact model is verified with TCAD simulations. Both model calculation and TCAD simulation results show that FWR variation significantly affects FinFET device behavior. The conventional short-channel model is inaccurate to describe the FWR effects. Several types of FWR functions are studied and important device parameters such as Vt.sat, Vt.lin, DIBL are extracted from TCAD simulations, all of which are found sensitive to FWR variation.
This paper presents a detailed characterization of silicon germanium oxide (SixGeyO1-x-y) thin films with an Oxygen
concentration below 10%. The results demonstrated that a high TCR and a low corresponding resistivity can be achieved
using various compositions, for example, Si0.054Ge0.877O0.069 film has achieved a TCR and a resistivity of -3.516/K, and
629 Ω-cm, respectively. The lowest measured resistivity and the corresponding TCR were 119.6 Ω-cm and -2.202 %/K
respectively, using Si0.136Ge0.838O0.026 for film deposited at room temperature, whereas the highest achieved TCR and the
corresponding resistivity at room temperature were -5.017 %/K, and 39.1×103 Ω-cm, respectively, using
Si0.167Ge0.762O0.071 for films deposited at room temperature. The calculated activation energy (Ea) from the slope of
Arrhenius plots were varied between 0.1232 eV to 0.3788 eV. The X-ray diffraction study demonstrated that the films
are amorphous but did not show any dependence on varying silicon at fixed oxygen concentration. The noise study
demonstrated that these films exhibit relatively high 1/f.
Thin film SixGe1-xOy infrared sensitive material was grown by RF magnetron sputtering, by depositing Si and Ge thin
film simultaneously from two deposition targets in an oxygen (O) and argon environment at room temperature and at
400°C. Film composition was varied by adjusting RF power applied to the silicon target and by varying the oxygen
flow of the gas mixture in the deposition chamber. The atomic compositions of Si, Ge, and O in the deposited thin film
were determined and analyzed using energy dispersive X-ray spectroscopy (EDS). The influence of changing Ge and
Si and O compositions on temperature coefficient of resistance (TCR), and resistivity were studied. Different
fabrication scenarios have been used to vary the Ge, Si and O concentrations. The highest achieved TCRs and the
corresponding resistivities at room temperature were -4.86 %/K and -6.43 %/K, and 2.45×102 Ω cm and 3.34×102 Ω
cm using Si0.195Ge0.706O0.099and Si0.127Ge0.835O0.038 for films deposited at room temperature and at 400 oC, respectively.
Thin film SixGe1-xOy were deposited on glass, silicon and SiO2 by RF magnetron sputtering using co-sputtering of silicon and germanium targets in an environment of oxygen and argon. Silicon percentage was varied from ~7% to 22%. Exact contents of each material were determined by XRD/EDS and electrical properties of amorphous
compound were studied. High values of temperature coefficient of resistance were obtained in specific conditions.
the highest achieved TCR at room temperature was (5.8%/K) using Si0.177Ge0.726O0.097 (film deposited at 400 °C).
The measured resistivity on this sample was 14.6 Ω cm.
A new micromachined one dimensional (1-D) micromirror array structure is presented that utilizes primarily
electroplated nickel, a mechanically durable material with a high glass transition temperature and with controllable
residual stress as the main structural material. The goal of this research is to develop custom micromirror array for use in
epitaxial growth systems to define the device structure and hence eliminate the need for etching and lithography, the
same micromirror can be used for switches and optical cross-connects. The high glass transition temperature of nickel
allows it to be used at high temperature without causing any contamination to the epitaxial systems or to the deposited
materials. Micromirror arrays with 5×5 and 1×5 pixels were designed with square shape with an area of 500 μm2 to
provide high fill factor and uniform stress distribution. The focus of this paper is on improved design for reducing
actuation voltage and increasing the rotation angle. The micromirror was previously fabricated using surface
micromachining technologies with a thick photoresist sacrificial layer [1]. The torsion beams were designed with a
serpentine shape in order to optimize the voltage necessary to tilt the micromirror by ± 10°. The micromirrors were
simulated using Coventor finite element tool in order to determine their geometries and performance. A voltage of 20
volts was required to rotate the mirror with a pixel pitch of 500 μm by 7.68° with resonance frequency of 221.52 Hz.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.