To fulfill Moore's law the R&D stage of 3x nm HP nodes will have to be reached in 2008. Conventional DUV
immersion technology is resolution limited to half pitch values exceeding 40 nm. Double Patterning Technology (DPT)
is a major candidate to reach the 3x nm node in time. Geometrical pattern split, doubling the pitch, is one of the major
steps of DPT. We present a feasibility study of the Rule Based (RB) DPT approach to pattern splitting based on a
representative and reviewed selection of clips and full-mask designs.
A methodology to predict the impact of mask overlay and litho-induced process variations on Statistical
Timing for Double Patterning is presented. As we migrate to the 32nm node and Double Patterning
techniques, Mask Makers, Ebeam providers and Scanner providers are given very aggressive requirements
for maintaining overlay accuracy. This method takes into account Mask CD Uniformity and Mask Image
placement error budgets presented in the 2006 ITRS. It is assumed the ITRS requirements are met. This
methodology combines the infrastructure used in Single Exposure Litho-Aware Layout Implementation
tools with Double Patterning decomposition results to determine a meaningful layout-specific analysis for
pre-tape-out timing sign-off. Traditional timing analysis uses a set of look-up tables for simulating device
distortions. These tables have been proven to require excessive guardbanding in Single Exposure masks.
Adding the additional dimension of overlay distortion to these tables will have the effects of hiding
parametric failures, or requiring excessive guardbanding to ensure timing predictability. Results will be
shown that describe the timing effects with and without taking into account these distortions, as well as
design samples that contribute to these distortions.
In conventional IC processes, the smallest size of any features that can be created on a wafer is severely limited by the pitch of the processing system. Double patterning technology is a key enabler of printing mask features on wafers as a hybrid extension to optical approaches with new litho-aware design methods and tools, optical equipment, and process flows. The approach does not require restrictions on the design of the chip. This paper will discuss the method and full-chip decomposition tool used to determine locations to split the layout. It will demonstrate examples of over-constrained layouts and how these configurations are mitigated. It will also show the reticle enhancement techniques used to process the split layouts and the Lithographic Checking. A new type of "hotspot" is identified through simulation and tools to identify, repair and verify are shown. Lithography results are shown with effective k1<0.2 for logic and flash memory patterns.
Trends in the design feature shrinking that outrun the progress in the lithography technologies require critical efforts in
the layout, process, and model development. Printing a layout is no longer a problem only for the lithographers; it has
penetrated into the layout stage as well. Layout patterns are getting more aggressive, raising serious printability
concerns. This requires very accurate models to analyze the manufacturability issues. This also often requires
simultaneous analysis and optimization of both layout and the process. Most advanced layout patterns are extremely
hard to manufacture and consequently run into the risk of re-spins. Therefore, an early pre-tapeout analysis and
troubleshooting of various layout, process, and RET issues has become a very important task. Our paper gives examples
of how these and other related issues can be addressed using a commercially available Design-for-Yield integrated
environment.
In conventional IC processes, the smallest size of any features that can be created on a wafer is severely limited by the
pitch of the processing system. This approach is a key enabler of printing mask features on wafers without requiring
new manufacturing equipment and with minor changes to existing manufacturing processes. The approach also does not
require restrictions on the design of the chip. This paper will discuss the method and full-chip decomposition tool used to
determine locations to split the layout. It will demonstrate examples of over-constrained layouts and how these
configurations are mitigated. It will also show the reticle enhancement techniques used to process the split layouts and
the Lithographic Checking used to verify the lithographic results.
The RET Design Flow has become a conglomeration of various point tools and methodologies. Deep sub-wavelength
DFM requirements have forced the design and manufacturing communities into very tight collaboration. EDA is also
driven to provide an infrastructure to facilitate communication for these communities. Having this infrastructure in
place has a direct impact on productivity and quality for which the value added is emphasized here.
Current generation photomasks use optical enhancements such as phase shifting and aggressive OPC in an effort to maintain image contrast as CDs shrink. The result is non-intuitive complex shapes with jogs and multiple levels with different materials. The mask repair engineer is challenged to work with defects that occur in ever tightening spaces on these complex masks. Prior established nanomachining technology allows nanometer level control of material removal. To date, the challenge in developing repair strategies that will meet transmission specifications as well as maintaining aerial image contrast through focus has been mainly an empirical exercise where the mask repair is attempted and aerial image measurement among other tests are used to verify the result. This approach can be streamlined by the use of lithography simulation which rigorously models the effects of mask defects on the aerial image at the wafer. Once the topography of the defect is measured by the nanomachining mask repair tool, lithography simulation can be proactively used to develop a repair strategy for the nanomachining process. Following this repair, the simulation software can then provide immediate feedback to confirm the post repair 3-D topology from AFM surface measurements for either approval or immediate rework. This integration is initially validated using a significant set of repairs with subsequent aerial image measurements compared to some of the more common evaluative analyses.
Photomask complexity threatens to outpace mask pattern generator productivity, as semiconductor devices are scaled down and optical proximity correction (OPC) becomes commonplace. Raster scan architectures are well suited to the challenge of maintaining mask throughput and mask quality despite these trends. The MEBES eXara mask pattern generator combines the resolution of a finely focused 50 keV electron beam with the productivity and accuracy of Raster Graybeam writing. Features below 100 nm can be imaged, and OPC designs are produced with consistent fidelity. Write time is independent of resist sensitivity, allowing high-dose processes to be extended, and relaxing sensitivity constraints on chemically amplified resists. Data handling capability is enhanced by a new hierarchical front end and hiearchical data format, building on an underlying writing strategy that is efficient for OPC patterns. A large operating range enables the MEBES eXara system to support the production of 100 nm photomasks, and the development of 70 nm masks.
The complexity of photomasks is rapidly increasing as semiconductor devices are scaled down and optical proximity correction (OPC) becomes commonplace. Raster scan architectures are well suited to the challenge of maintaining mask throughput despite these trends. Electron-beam techniques have the resolution to support OPC requirements into the foreseeable future. The MEBES® eXara mask pattern generator combines the resolution of a finely focused electron probe with the productivity and accuracy of Raster Graybeam patterning. Features below 100nm can be created, and OPC designs are produced with consistent fidelity. Write time is independent of resist sensitivity, allowing high-dose processes to be extended, and relaxing sensitivity constraints on advanced chemically amplified resists. The system is designed for the production of 100nm photomasks, and will support the development of 70nm masks.
Photomask complexity increases rapidly as semiconductor devices continue to shrink and as optical proximity correction becomes commonplace. This trend stresses the performance of mask pattern generators due to the increase in both primary and subresolution features. However, the next-generation MEBES raster scan architecture is well-suited to the challenge of maintaining throughput regardless of increases in pattern complexity. In addition, this new system provides an operating envelope that is sufficiently broad to expose all practical resist materials with a fixed number of writing passes. Write time is independent of material sensitivity, which has the benefits of allowing high-dose processes to be optimized, and also of supporting a wide selection of chemically amplified resist candidates for critical mask patterning. The new system shows the promise of being extendible to the 70 nm technology generation.
This paper describes improvements in column design and writing strategy that, together, enable mask production for the 130 nm technology node. The MEBESR 5500 system employs a new high-dose electron gun and column design. We summarize experiments relating lithographic quality to increased dose and the effects of spot size and input address on lithography. These experiments are performed with ZEP 7000 resist and dry etch. A new graybeam writing strategy, Multipass Gray-II (MPG- II), is described in detail. This strategy creates eight dosed gray levels and provides increased writing throughput (up to 8X, compared to single-pass printing) without loss of lithographic quality. Significantly, critical dimension (CD) uniformity, butting, and other important specifications are improved with MPG-II. Lithographic results and throughput data are reviewed. A consequence of the improvement in CD control and throughput is greater productivity for 180 nm devices.
Etec Systems, Inc. has developed a new e-beam mask lithography system, the MEBES 4500S, featuring a higher productivity writing strategy called multipass gray and a number of mechanical and electrical improvements. This new system, based on the proven technologies introduced in the MEBES 4500 system, provides improved throughput and accuracy. The MEBES 4500S system with multipass gray supports smaller mask design addresses needed for high resolution masks, while providing higher dose for high contrast processes with low sensitivity and improved CD linearity. Improved print performance is achieved by the introduction of several system design changes that work in conjunction with the multipass gray writing mode. These changes include improved column deflection system temperature control, enhanced TFE current control, improved work chamber thermal management, and improved stage drive vibration damping. Details of these features are presented along with first performance data for the new system.
The design rule requirements and error budget allocation for maskmaking have made the mask a critical component in the fabrication of 250 nm design rule IC devices. The MEBES 4500 raster-scan reticle writer was designed to meet the mask requirements for pilot production of this generation of devices. In this paper, we will review the IC device and user requirements that drove the design criteria of the MEBES 4500 system. The architecture of the MEBES 4500 system is described and compared to these design criteria. MEBES 4500 perfonnance results during development, manufacture, and installation are also compared to the commercial requirements of 250 nm design rule ICs.
MEBES systems are characterized by constituent error performance, whereas masks produced on pattern generators are characterized by composite error performance. System evaluation by constituent specification is notable for the ease with which system calibration can be obtained, monitored, and maintained. Constituent specifications need to be retained for these reasons. This work investigates the composite performance of a MEBES 4500 system when generating masks compared to system constituent performance. Masks with scan-centered and non-scan- centered patterns are characterized and compared with both MEBES-based MARKET metrology and independent tool-based metrology.
It has been shown that mask composite pattern position errors can be reduced by more than 40% on the MEBES 4000 system if a reference grid is used to match a MEBES 4000 system to an independent metrology tool. It has also been shown that matching between MEBES systems can be significantly improved by use of the dynamic grid matching (DGM) feature of the MEBES 4500 system. Several methods of grid matching are possible on the MEBES 4500 tool, including generation of a physical reference artifact or 'golden plate.' This work defines a method to produce a golden plate artifact for use in system grid matching. The technique uses a second level (phase shift mask) alignment capability to a zero level target to place a reference grid pattern on the reticle. Subsequent exposures of this pattern overlaid on the same substrate with different orientations serve to reduce systematic and random errors of the exposure tool. The processed image can then be used as a reference artifact for different systems. If necessary, the procedure can be iterated to further improve accuracy. Results of this methodology to produce an artifact are presented as well as its application in system matching to reduce composite positional errors as measured by independent metrology tools.
Techniques have been developed that can quickly and accurately measure corner rounding and contact fill as key indicators of pattern fidelity. Using these techniques, we have examined writing variables for their effect on the lithographic quality of 1.0 micrometers contact. A small contact is perhaps the most demanding figure to achieve, so the results shown can be considered the worst case for 4X radicle manufacturing at 250 nm design rules. A MEBES 4500 was used as the writing tool, using PBS resist on quartz masks. Standard printing methods, single-phase printing (SPP) and multiphase printing (2X MPP) were examined. Results indicate that excellent corner rounding results can be achieved with small address sizes, regardless of the writing strategy or the dose used. As expected, larger spot sizes increase the amount of corner rounding, regardless of the address. As the pattern address is increased, judicious choices of spot size reduce potential pattern fidelity loss when imaging small contracts and other fine features. Multiphase printing is a technique that offers advantages to the user. Its use of offset scan voting (OSV) is a significant factor in reducing placement errors. MPP (2X) has an additional advantage of providing higher dosages. This provides flexibility in resist choices and in the selection of a process window. With 2X MPP, the user has a wide range of addresses and spot sizes that will give excellent results. The dynamic range of operating conditions possible with 2X MPP when writing 1.0 micrometers contacts is a reduced subset of those available using SPP, due to the 2X writing grid (output address). Implementation of 2X MPP has been limited on previous MEBES models due to increased write times of multipass writing. The MEBES 4500 data path supports 2X MPP with write times that approximate SPP. The practical operating envelope of both writing strategies are detailed in this paper. Overall, the MEBES 4500 has a large dynamic operating range. When used with a high resolution process, MEBES 4500 provides excellent pattern fidelity to support requirements of 250 nm design rules.
Performance of a MEBES tool depends in part on how well it is optimized for a particular user application. This paper examines the efforts made to optimize a MEBES 4000 at Intel to meet performance goals of 350 nm design rules. The areas of particular concern are critical dimension, resolution, and composite positional accuracy. PBS resist processes and cassette- specific corrections (CAZOC) for six cassettes are examined to meet these goals. As part of a SEMATECH development program, a MEBES 4000 system at Etec is being upgraded to a MEBES 4500. The performance of the tool is characterized at each incremental phase of the upgrade. Results show that significant advances have been made in accuracy, system calibration and control, and data path.
New MEBES reticle writers are described that meet the production requirements of the 350- nm and 250-nm design rules required for 64 Mb and first generation 256 Mb DRAM techniques. These raster scan e-beam systems are based on the MEBES IV thermal field emission (TFE) exposure system, in production use since early 1992. The MEBES IV-TFE system exceeds its 500-nm design rule requirement and is routinely used to product reticles of first-generation 64 Mb DRAMs, prototype 256 Mb DRAMs, and phase shift masks. The success of MEBES IV-TFE is based on a close working relationship with system users, who provided input to establish the requirements of the new reticle writers. The new reticle writers are the result of a two-phase development program. The initial phase, completed in 1993, focused on productivity improvements to the base system, which proved to have excellent accuracy. These improvements ease the handling of the large pattern files, improve the use of the 160 MHz writing rate with a faster data path and more efficient writing strategy, and improve overall system utilization with in situ (maskless) beam-calibration techniques. The second phase of development, completed early in 1994, focused on the production reticle requirements of second-generation 64 Mb DRAM, including optical proximity correction features, and first-generation 256 Mb DRAM. The second development phase improves data path speed, system accuracy, and system productivity. System and subsystem performance is shown for the first and second development phases. Lithographic and write-time performance on the product is presented and discussed in the context of system requirements.
The fabrication of phase shifting masks requires precise alignment between the primary and shifter layers. The MEBESR IV electron-beam lithography system uses its SEM mode to acquire a video image of the phase shift mask (PSM) alignment mark. Digital signal- processing algorithms have been developed to accurately determine the locations of the marks. Alignment marks are acquired through various resist systems and film thicknesses. Machine control software translates and rotates the MEBES coordinate system to align it with the mask coordinate system, as determined by the location of the alignment marks. Results showing overlay accuracy between layers are presented.
Alignment is the dominant performance issue for photolithography tools as integrated circuit feature sizes approach 500 nm. A study is presented on two new types of alignment structures for use with scribelines of lOOjim or less using a 1X wafer stepper with through the reticle and through the lens alignment with darkfield detection. Single line alignment structures represent a continuation of prior work1 which uses system software to automatically characterize signal strength and process latitude. Multiline pseudorandom ( MPR ) alignment structures are introduced which provide increased signal intensity. Darkfield target illumination is introduced and is shown to enhance target capture. The application of these new alignment structures for use with deep UV (DUV) and other situations is reviewed.
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