Double-patterning lithography / double-exposure lithography is believed to be a solution in order to enable the
32nm-Half-Pitch (HP) and below process node until EUV lithography infrastructure is ready. However, one of the
biggest challenges is the overlay budget along with critical dimension (CD) control. In this paper, we propose that
instead of using multiple masks for the DPL (STD DPL), multiple split patterns are printed on a single mask so that each
pattern is separately or simultaneously exposed onto a wafer in order to reduce the mask-to-mask overlay error. This can
also reduce the mask cost and mask manufacturing time compared with STD DPL, at the expense of reducing
manufacturing throughput. We propose two ideas about how to place the split patterns in a single mask and simulate
corresponding shot throughput comparisons. The results show that by using multi-layer reticle (MLR) strategy for
splitting the original layout into 2 split patterns onto a single mask (Method I), we achieve: 1) reduction of the
mask-to-mask overlay error factor 2) use of a single mask (reducing mask costs) and 3) reduction of wafer shot
throughput to roughly 50% of that achieved by STD DPL. Also by using our new approach of placing multiple-split
patterns to form the arrays within the mask scribe (Method II), we achieve: 1) reduction of the mask-to-mask overlay
error factor 2) use of a single mask (reducing mask costs) and 3) drastically improved wafer shot throughput (at least
90% of the STD DPL, 180% of Method I).
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