Mr. Romain J. Lallement Profile

Romain J. Lallement

at IBM

SPIE Involvement:

Conference Program Committee | Author

Romain Lallement is currently Mask and Patterning Technical Project Leader at IBM’s AI Hardware Center where he leads mask technology development and introduces them into IBM’s test site pipeline. This central role in IBM’s Nanotechnology Laboratory relies on a holistic understanding of advanced photolithography, mask processes, and technology node requirements to support IBM’s roadmap. Recently, Romain achieved extreme ultraviolet (EUV) mask process qualification to enable single exposure yield at 30nm pitch, as well as seamless mask technology introduction for IBM International Semiconductor Development Alliance (ISDA) into leading edge Gate All Around (GAA) technology.
Prior to serving as Mask and Patterning Technical Project Leader, Romain held several team lead positions within ISDA. Working alongside partners from every aspect of the industry, he has managed projects of highly skilled multidisciplinary engineers in photo lithography, reactive ion etching, wet etching and device, contributing to Design Technology Co Optimization (DTCO) across the device Front End of the Line (FEOL), and as well as leading the patterning team test site install. In this role Romain developed key aspect of the spacer, work function metal module, leading to the success of the NanoSheet device architecture for 5 nm and beyond.
Romain holds a master’s degree in Material Science from Polytech Marseille, France. After graduating, Romain joined STMicroelectronics where he worked in R&D as photo lithography engineer on Complementary metal–oxide–semiconductor (CMOS) and embedded nonvolatile memory (eNVM) technology. He has qualified technologies to the highest standards of quality for the most stringent applications in automotive and bio-medical technology. He also successfully managed the transition of an entire manufacturing site to a new APC system significantly improving fab metrics. Romain has co-authored several published articles and holds 7 patents in the US and internationally

Proceedings Article | 12 November 2024 Presentation + Paper

Low-n absorber EUV masks: mask manufacturing assessment through process characterization and optimization with early look at EUV Low-NA and High-NA imaging performance

Henry Kamberian, Jed Rankin, Jinju Beineke, Romain Lallement, Michael Green, Martin Burkhardt, Mohamed Ramadan, Scott Halle, Rajiv Sejpal, Oseo Park, Sriharsha Sudhindra, Chris Progler

Proceedings Volume 13216, 132160C (2024) https://doi.org/10.1117/12.3037087

KEYWORDS: Photomasks, Extreme ultraviolet, Extreme ultraviolet lithography, Etching, Semiconducting wafers, Electron beam lithography, Optical lithography, Manufacturing, Photoresist processing, Photomask technology

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Industry has made significant progress advancing EUV Lithography technology for the past several years leading to its full adoption starting at N7 node and volume production through N3 node. To extend EUVL technology well into sub-2nm node regime and beyond, a new High NA EUV platform (Hi-NA) is needed and will be introduced. These new Hi-NA scanner platforms will use anamorphic optics with 0.55NA with EUV illumination incidence angle lower from current scanners arriving light of 6° incidence. At mask level, the combination of EUV light at oblique incidence, absorber thickness, and non-uniform mirror reflectance through incidence angle, creates mask-induced imaging aberrations, known as mask 3D effects (M3D). Additionally, these Hi-NA systems introduce mask related imaging complications such as non-telecentricity, which has shown to cause H-V bias due to shadowing, pattern shift through focus, and image contrast loss due to apodization by the reflective mask coatings. All these factors suggest a need for novel EUV mask absorbers, which will reduce these effects. Of the various novel materials, the low refractive index (low-n) absorber materials, characterized as EUVPSM, have received most attention and acceptance. EUVPSM promises to address mask 3D effects while improving wafer image quality with enhanced contrast. In this work, we have embarked on characterization studies to evaluate a EUV low-n absorber material (EUVPSM), which meets EUV mask fabrication requirements for impending 2nm and below advanced semiconductor device nodes. While a number of low-n materials were considered, through simulation and material evaluation the selection was narrowed to one material, which met thickness, PSM phase angle, and EUV reflectivity targets. Characterization consisted of studying mask manufacturing modules including patterning, post-exposure processing, cleaning, defect inspection and repair. In this study, the material was evaluated for critical patterning performance looking at key CD control metrics such as resolution, uniformity, linearity, proximity and LER/LWR. We also characterized pattern fidelity looking at complex mask designs for 2nm node class and beyond using internally developed advanced mask characterization and optimization methodology emphasizing 2D pattern characterization, including sidewall angle (SWA) assessment of patterned absorber and resultant imaging. Another module studied is the EUV Black-Border patterning process which must improve to meet tightening dimensional, placement and EUV reflectivity controls needed for the Hi-NA regime, especially to enable half-field stitching requirements. With a mask manufacturing process established and characterized, EUVPSM mask lithographic performance was evaluated both to validate the simulation models, and to assess overall EUV printability at Low-NA, where the lithography process and tools are more established. Additionally, an early assessment at Hi-NA conditions is planned to examine critical imaging metrics while comparing the EUVPSM to standard Ta-based binary mask absorber, including early assessment of BB process on both mask and wafer.

Proceedings Article | 21 November 2023 Presentation + Paper

EUV mask patterning process to enable opaque SRAFs for bright field EUV mask imaging

Michael Green, Scott Halle, Mohamed Ramadan, Romain Lallement, Henry Kamberian, Martin Burkhardt, Jinju Beineke, Jed Rankin, Chris Progler, Steven McDermott

Proceedings Volume 12751, 127510M (2023) https://doi.org/10.1117/12.2689665

KEYWORDS: SRAF, Extreme ultraviolet, Optical lithography, Resolution enhancement technologies, Opacity, Extreme ultraviolet lithography, Optical proximity correction, Line edge roughness, Semiconducting wafers, Printing

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As extreme ultraviolet lithography (EUVL) technology progresses to support more advanced nodes, mask designs are becoming more complex and difficult for mask makers to produce with the required fidelity. Resolution enhancement techniques (RETs) including mask optical proximity correction (OPC) models and the addition of sub-resolution assist features (SRAFs) are now critical technology enablers. Early adopters of EUVL benefited from the resolution improvement provided by the shorter wavelength. To extend the benefits of EUV to smaller technologies and broader applications, SRAFs are valuable tools to maximize the process window for a variety of critical layers which require both bright and dark field imaging. Regardless of mask tone, because of the short wavelength of EUV radiation, very small SRAFs are required, thus patterning SRAFs for EUVL poses significant mask process challenges. E beam exposure and resist characteristics are key factors for important patterning attributes including minimum resolvable size, line edge roughness (LER), corner rounding (CR), and line end shortening (LES). Patterning dark SRAFs for bright field masks involves an additional challenge of overcoming mechanical forces on these small structures that can cause feature toppling or collapse. In this study, we demonstrate a mask process capable of patterning dark SRAFs on mask at line widths below 25nm (4X). We will discuss patterning solutions including innovations in both the physical mask manufacturing processes as well as mask data preparation techniques, such as mask process correction (MPC). We will utilize advanced characterization techniques to evaluate SRAF pattern fidelity on the mask and its predicted impact on wafer printing performance. A process capable of resolving sufficiently small SRAFs enables an on-wafer analysis to validate whether the predicted lithographic benefits can be demonstrated. Finally, we will review the outlook of continued shrinking mask resolution requirements from both a design value and process implementation perspective. The coming challenges for EUV mask makers include supporting not only ever increasing design complexity, but also the introduction of new mask materials, including phase shift masks (PSMs) as part of the overall RET solution.

Proceedings Article | 28 April 2023 Presentation + Paper

Impact of high-NA half-field to full-field overlay performance by Monte Carlo simulations

Romain Lallement, Daniel Schmidt, Richard Johnson, Jack Wong, Christopher Carr, Martin Burkhardt, Jaime Morillo, Allen Gabor

Proceedings Volume 12494, 124940S (2023) https://doi.org/10.1117/12.2661339

KEYWORDS: Monte Carlo methods, Extreme ultraviolet lithography, Scanners, Deep ultraviolet, Design and modelling, Semiconducting wafers, Overlay metrology, Photomasks, Extreme ultraviolet, Error analysis

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Proceedings Article | 13 June 2022 Presentation

OVL performance of HighNA stitched fields using Monte Carlo simulations

Romain Lallement, Jaime Morillo, Daniel Schmidt, Rick Johnson, Cody Murray, Martin Burkhardt, Allen Gabor

Proceedings Volume PC12051, PC120510R (2022) https://doi.org/10.1117/12.2614278

KEYWORDS: Monte Carlo methods, Scanners, Extreme ultraviolet lithography, Overlay metrology, Semiconducting wafers, Photomasks, Optical lithography, Manufacturing, Lithography, Extreme ultraviolet

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Proceedings Article | 13 June 2022 Presentation

Resist shrink characterization methodology for more accurate CD metrology

Mary Breton, Karen Petrillo, Jennifer Church, Luciana Meli, Jennifer Fullam, Stuart Sieg, Romain Lallement, Nelson Felix, Shimon Levi, Susan Zollinger, Felix Levitov, Sean Hand, Jason Osborne, Weijie Wang

Proceedings Volume PC12053, PC120530C (2022) https://doi.org/10.1117/12.2614219

KEYWORDS: Critical dimension metrology, Metrology, Scanning electron microscopy, Photoresist materials, Optical proximity correction, Process modeling, Data modeling, Photomasks, Lithography, Extreme ultraviolet lithography

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Proceedings Article | 26 May 2022 Presentation + Paper

Focus considerations of design pitches and absorber choice for EUV random logic

Martin Burkhardt, Zheng Chen, Scott Halle, Romain Lallement, Stuart Sieg, Luciana Meli

Proceedings Volume 12051, 120510C (2022) https://doi.org/10.1117/12.2614296

KEYWORDS: Nickel, Photomasks, Extreme ultraviolet, SRAF, Phase shifts, Absorption, Diffraction, Optical lithography, Tantalum

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Proceedings Article | 17 November 2021 Presentation + Paper

Exploring the stochastics cliff: understanding the impact of LER/LWR to stochastic defectivity and yield

Jennifer Church, Graham Jensen, Romain Lallement, Andrew Cross, Luciana Meli

Proceedings Volume 11854, 118540X (2021) https://doi.org/10.1117/12.2600877

KEYWORDS: Line edge roughness, Stochastic processes, Inspection, Modulation, Critical dimension metrology, Semiconducting wafers, Plasma, Defect inspection, Optical inspection, Extreme ultraviolet lithography

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Proceedings Article | 9 March 2021 Presentation + Paper

Effect of high NA “half-field” printing on overlay error

Allen Gabor, Martin Burkhardt, Romain Lallement, Jaime Morillo, Chris Robinson, Daniel Schmidt

Proceedings Volume 11609, 1160907 (2021) https://doi.org/10.1117/12.2581823

KEYWORDS: Printing

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Proceedings Article | 22 February 2021 Presentation

The road towards aggressive pitch scaling with single exposure EUV

Luciana Meli, Jennifer Church, Anuja De Silva, Karen Petrillo, Dario Goldfarb, Stuart Sieg, Romain Lallement, Dallas Lea, Martin Burkhardt, Nelson Felix, Cody Murray

Proceedings Volume 11609, 116090P (2021) https://doi.org/10.1117/12.2583566

KEYWORDS: Extreme ultraviolet lithography, Roads, Extreme ultraviolet, Optical lithography, Yield improvement, Transistors, Printing, Modulation, Metals, Materials processing

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SPIE Journal Paper | 1 July 2020 Open Access

Fundamental characterization of stochastic variation for improved single-expose extreme ultraviolet patterning at aggressive pitch

Jennifer Church, Luciana Meli, Jing Guo, Martin Burkhardt, Chris Mack, Anuja De Silva, Karen Petrillo, Mary Breton, Ravi Bonam, Romain Lallement, Eric Miller, Brad Austin, Shravan Matham, Nelson Felix

JM3, Vol. 19, Issue 03, 034001, (July 2020) https://doi.org/10.1117/12.10.1117/1.JMM.19.3.034001

KEYWORDS: Stochastic processes, Fiber optic illuminators, Line edge roughness, Critical dimension metrology, Defect inspection, Extreme ultraviolet, Inspection, Optical lithography, Yield improvement

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Proceedings Article | 23 March 2020 Presentation + Paper

EUVL mask process development and verification using advanced modeling and characterization techniques

Michael Green, Romain Lallement, Mohamed Ramadan, Derren Dunn, Henry Kamberian, Stuart Sieg, Young Ham, Chris Progler

Proceedings Volume 11323, 113230Q (2020) https://doi.org/10.1117/12.2560545

KEYWORDS: Photomasks, Semiconducting wafers, Extreme ultraviolet lithography, Scanning electron microscopy, Line edge roughness, Stochastic processes, Optical proximity correction, SRAF, Metals, Lithography

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Mask technology is key to enabling the progression of advanced IC technology nodes into the realm beyond 7nm node logic. In particular, extreme ultraviolet lithography (EUVL) relies heavily on the mask in order to achieve adequate process window (PW) and final yields. In the EUVL environment, mask process development and verification becomes increasingly more difficult and costly. The mask manufacture costs are driven by multiple factors including significantly more expensive mask blanks and increased ebeam write times. Wafer verification of mask process improvements is very difficult with the relatively low number of early adopters of EUVL and high cost associated with processing non-product wafers with that technology. It is therefore useful for mask manufacturers and wafer lithographers to collaborate to develop low cost mask process screening techniques as a precursor to committing valuable EUV exposure time for final verification. Previously, we demonstrated that by utilizing a toolkit of mask and wafer analytical techniques known as advanced mask characterization and optimization (AMCO) [2], we were able to predict wafer defectivity on 1D and 2D metal structures and optimize a mask process to enable 30nm pitch interconnect in a single exposure step using EUVL [1]. In this study, we use similar methodology to develop a mask process for beyond 7nm node logic contact and via layers. These structures pose a different set of challenges than the metal layer. Contact hole area loss, corner rounding (CR), and mask process-induced x-y error on asymmetric holes must be optimized to deliver the required capability. Additionally, sub-resolution assist features (SRAFs) become relevant at this node. Resolving these on the mask is critical. Here, we describe the development of a mask process to overcome these challenges. We use advanced modeling techniques including AMCO to characterize the process improvements and predict wafer performance. Mask process improvements that are characterized include both physical mask process components as well as write data optimization techniques, i.e. mask process correction (MPC).

Proceedings Article | 23 March 2020 Presentation + Paper

Fundamental characterization of stochastic variation for improved single-expose EUV patterning at aggressive pitch

Jennifer Church, Luciana Meli, Jing Guo, Martin Burkhardt, Chris Mack, Anuja DeSilva, Karen Petrillo, Mary Breton, Ravi Bonam, Romain Lallement, Eric Miller, Brad Austin, Shravan Matham, Nelson Felix

Proceedings Volume 11323, 113230O (2020) https://doi.org/10.1117/12.2551487

KEYWORDS: Stochastic processes, Line edge roughness, Inspection, Defect inspection, Critical dimension metrology, Extreme ultraviolet, Optical lithography, Etching, Bridges

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Proceedings Article | 13 March 2015 Paper

EUV processing and characterization for BEOL

Nicole Saulnier, Yongan Xu, Wenhui Wang, Lei Sun, Lin Lee Cheong, Romain Lallement, Genevieve Beique, Bassem Hamieh, John Arnold, Nelson Felix, Matthew Colburn

Proceedings Volume 9422, 94220T (2015) https://doi.org/10.1117/12.2086126

KEYWORDS: Semiconducting wafers, Etching, Line edge roughness, Line width roughness, Extreme ultraviolet lithography, Extreme ultraviolet, Critical dimension metrology, Scanning electron microscopy, Lithography, Scanners

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Proceedings Article | 14 October 2011 Paper

Anticipation of dimensional issues caused by topography during photo lithography

Lionel Ravel, Christophe Brault, Chloé Hegaret, Antonio Di Giacomo, Romain Lallement, Jérôme Azémar, Marie Hellion

Proceedings Volume 8166, 81663J (2011) https://doi.org/10.1117/12.896827

KEYWORDS: Transistors, Critical dimension metrology, Photomasks, Lithography, Optical proximity correction, Etching, Reflectivity, Photoresist materials, Semiconducting wafers, Scanning electron microscopy

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Proceedings Article | 2 April 2011 Paper

DOE experiment for scattering bars optimization at the 90nm node

G. Bouton, B. Connolly, D. Courboin, A. Di Giacomo, F. Gasnier, R. Lallement, D. Parker, M. Pindo, J. C. Richoilley, F. Royere, A. Rameau-Savio, M. Tissier

Proceedings Volume 7985, 79850R (2011) https://doi.org/10.1117/12.896341

KEYWORDS: Photomasks, Critical dimension metrology, Inspection, Diffractive optical elements, Optical proximity correction, Scattering, Scanning electron microscopy, Semiconducting wafers, Lithography, Manufacturing

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Scattering bars (SB) are sub-resolution lines added to the original database during Resolution Enhancement Techniques (RET) treatments. Their goal is stabilizing the CD of the adjacent polygons (by suppressing or reducing secondary diffraction waves). SB increase the process window in the litho process by lowering the first derivative of the CD. Moreover, the detailed knowledge of SB behavior around the fab working point is a must for future shrinks and for preparing the next technology nodes. SB are inserted in the generation of critical levels for STMicroelectronics 90 nm technology embedded memories before invoking the Model for Optical Proximity Corrections (MBOPC). This allows the software to calculate their contribution to the intensity in the aerial image and integrate their effects in Edge Proximity Error (EPE) corrections. However the Rule-Based insertion of these assist features still leaves behind occurrences of conflicting priorities as in the image below. (See manuscript PDF)Detection of Hot Spots in 2D simulations for die treatment validation (done on BRION equipment on each critical level before mask making) is in most cases correlated with SB singularities, at least for CD non-uniformity, bridging issues and necking in correspondence with OPC fragmentation effects. Within the framework of the MaXSSIMM project, we established a joint STMicroelectronics and Toppan Photomasks team to explore the influence of assist features (CD, distance), convex and concave corner rounding and CD uniformity by means of specific test patterns. The proposed study concerns the algorithms used to define the mask shop input as well as the physical mask etching. A set of test cases, based on elementary test patterns, each one including a list of geometrical variations, has been defined. As the number of configurations becomes rapidly very large (tens of thousands) we had to apply Design of Experiments (DOE) algorithms in order to reduce the number of measurements to a reasonable range (a few hundred). The proposed test cells have been inserted in the scribe lanes of an engineering Gate mask of one of STMicroelectronics' high volume products. Real Hot Spots, detected in the product chosen as the test vehicle, have also been submitted to the same variations and inserted in scribe blocks. In parallel with OPC-like scribe layouts, four best-guess treatments were applied, on the same critical mask, to assess transistor performance and yield impact by standard wafer splitting on engineering lots. The advanced binary 4×6" reticle for 193nm exposure has been manufactured by Toppan Photomasks in the AMTC facility in Dresden using the standard production process on the NuFlare5000 e-beam writing platform. The exploration of the parameter space around the current working point will determine if the current process settings already represent an optimum or if there is room for significant improvement of the wafer manufacturing process.

Showing 5 of 15 publications

Conference Committee Involvement (4)

Photomask Technology 2024

30 September 2024 | Monterey, California, United States

Photomask Technology 2023

2 October 2023 | Monterey, California, United States

Photomask Technology 2022

26 September 2022 | Monterey, California, United States

Photomask Technology

27 September 2021 | Online Only, United States

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