The IUCAA digital sampling array controller (IDSAC) is a flexible and generic yet powerful CCD controller that can handle a wide range of scientific detectors. Based on an easily scalable modular backplane architecture consisting of single board controllers (SBC), IDSAC can control large detector arrays and mosaics. Each of the SBCs offers the full functionality required to control a CCD independently. The SBCs can be cold swapped without the need to reconfigure them. IDSAC is also available in a backplane-less architecture. Each SBC can handle data from up to four video channels with or without dummy outputs at speeds up to 500-kilo pixels per second (kPPS) per channel with a resolution of 16 bits. Communication with a Linux-based host computer is through a USB3.0 interface, with the option of using copper or optical fibers. A field programmable gate array (FPGA) is used as the master controller in each SBC, which allows great flexibility in optimizing performance by adjusting gain, timing signals, bias levels, etc., using user-editable configuration files without altering the circuit topology. Elimination of thermal kTC noise is achieved via digital correlated double sampling (DCDS). The number of digital samples per pixel (for both reset and signal levels) is user configurable. We present the results of noise performance characterization of IDSAC through simulation, theoretical modeling, and actual measurements. The contribution of different types of noise sources is modeled using a tool to predict noise of a generic DCDS signal chain analytically. The analytical model predicts the net input referenced noise of the signal chain to be 5 electrons for 200-k pixels/s per channel readout rate with three samples per pixel. Using a cryogenic test setup in the lab, the noise is measured to be 5.4 e (24.3 μV), for the same readout configuration. With a better-optimized configuration of 500-kPPS readout rate, the measured noise is down to 3.8 electrons RMS (17 μV), with three samples per interval.
The South African Astronomical Observatory (SAAO) is currently developing WiNCam, the Wide-field Nasmyth Camera, to be mounted on Lesedi, the observatory’s new 1-metre telescope. This paper discusses the design and results for the remotely-operated camera system. The camera consists of an E2V-231-C6 Back Illuminated Scientific Charge Coupled Device (CCD) sensor with 6144x6160 pixels, four outputs operating in non-inverted mode. This is to date the largest single chip CCD-system developed at SAAO. The CCD is controlled with a modified Inter-University Centre for Astronomy and Astrophysics (IUCAA) Digital Sampler Array Controller (IDSAC) utilizing digital correlated double sampling. The camera system will have full-frame and frame-transfer read out modes available with sub-windowing and pre-binning abilities. Vacuum through-wall PCB technology is used to route signals through the vacuum interface between the controller and the CCD. A thin, compact, 125x125mm aperture, sliding-curtain-mechanism shutter was designed and manufactured together with a saddle-type filter-magazine-gripper system. The CCD is cryogenically cooled using a Stirling Cooler with active vibration cancellation; CCD temperature control is done with a Lake Shore Temperature Controller. A Varian Ion Pump and Activated Charcoal are used to maintain good vacuum and to prolong intervals between vacuum pump down. The various hardware components of the system are connected using distributed software architecture, and a web-based GUI allows remote and scripted operation of the instrument.
KEYWORDS: Sensors, Wavefront sensors, Control systems, Analog electronics, Multiplexers, Stars, Field programmable gate arrays, Power supplies, Electrons, Interfaces
As a part of a design study for the On-Instrument Low Order Wave-front Sensor (OIWFS) for the TMT Infra-Red Imaging Spectrograph (IRIS), we recently evaluated the noise performance of a detector control system consisting of IUCAA SIDECAR DRIVE ELECRONICS CONTROLLER (ISDEC), SIDECAR ASIC and HAWAII-2RG (H2RG) MUX. To understand and improve the performance of this system to serve as a near infrared wavefront sensor, we implemented new read out modes like multiple regions of interest with differential multi-accumulate readout schemes for the HAWAII-2RG (H2RG) detector. In this system, the firmware running in SIDECAR ASIC programs the detector for ROI readout, reads the detector, processes the detector output and writes the digitized data into its internal memory. ISDEC reads the digitized data from ASIC, performs the differential multi-accumulate operations and then sends the processed data to a PC over a USB interface. A special loopback board was designed and used to measure and reduce the noise from SIDECAR ASIC DC biases2. We were able to reduce the mean r.m.s read noise of this system down to 1-2 e. for any arbitrary window frame of 4x4 size at frame rates below about 200 Hz.
ISDEC-2 - IUCAA1 SIDECAR Drive Electronics Controller is an alternative for Teledyne make JADE2 based controller for HAWAII detectors. It is a ready to use complete package and has been developed keeping in mind general astronomical requirements and widely used observatory set-ups like preferred OS-Linux , multi-extension fits output with fully populated headers (with detector as well as telescope and observation specific information), etc. Actual exposure time is measured for each frame to a few tens of microsecond accuracy and put in the fits header. It also caters to several application specific requirements like fast resets, strip mode, multiple region readout with on board co-adding, etc. ISDEC-2 is designed to work at -40 deg. and is already in use at observatories worldwide. ISDEC-3 is an Artix-7 FPGA based SIDECAR Drive Electronics Controller currently being developed at IUCAA. It will retain all the functionality supported by ISDEC-2 and will also support the operation of H2RG in continuos, fast (32 output, 5 MSPS, 12 bit) mode. It will have a 5 Gbps USB 3.0 PC interface and 1 Gbps Ethernet interface for image data transfer from SIDECAR to host PC. Additionally, the board will have DDR-3 memory for on-board storage and processing. ISDEC-3 will be capable of handling two SIDECARs simultaneously (in sync) for H2RG slow modes.
SIDECAR is an Application Specific Integrated Circuit (ASIC), which can be used for control and data acquisition from
near-IR HAWAII detectors offered by Teledyne Imaging Sensors (TIS), USA. The standard interfaces provided by
Teledyne are COM API and socket servers running under MS Windows platform. These interfaces communicate to the
ASIC (and the detector) through an intermediate card called JWST ASIC Drive Electronics (JADE2). As part of an
ongoing programme of several years, for developing astronomical focal plane array (CCDs, CMOS and Hybrid)
controllers and data acquisition systems (CDAQs), IUCAA is currently developing the next generation controllers
employing Virtex-5 family FPGA devices. We present here the capabilities which are built into these new CDAQs for
handling HAWAII detectors. In our system, the computer which hosts the application programme, user interface and
device drivers runs on a Linux platform. It communicates through a hot-pluggable USB interface (with an optional
optical fibre extender) to the FPGA-based card which replaces the JADE2. The FPGA board in turn, controls the
SIDECAR ASIC and through it a HAWAII-2RG detector, both of which are located in a cryogenic test Dewar set up
which is liquid nitrogen cooled. The system can acquire data over 1, 4, or 32 readout channels, with or without binning,
at different speeds, can define sub-regions for readout, offers various readout schemes like Fowler sampling, up-theramp
etc. In this paper, we present the performance results obtained from a prototype system.
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