KEYWORDS: Optical alignment, Carbon, Etching, Optical lithography, System on a chip, Near infrared, Overlay metrology, Resistance, Lithography, Semiconducting wafers
Hardmask processes are a key technique to enable low-k semiconductors, but they can have an impact on patterning control, influencing defectivity, alignment, and overlay. Specifically, amorphous carbon layer (ACL) hardmask schemes can negatively affect overlay by creating distorted alignment signals. A new scheme needs to be developed that can be inserted where amorphous carbon is used but provide better alignment performance. Typical spin-on carbon (SOC) materials used in other hardmask schemes have issues with DCD-FCD skew. In this paper we will evaluate new spin-on carbon material with a higher carbon content that could be a candidate to replace amorphous carbon.
Wafer topography structures in the implant lithography process, which include the shallow trench isolation and the poly
gate, can result into a severe degradation of the resist profile and significant critical dimension variation. While bottom
anti-reflective coating (BARC) is not suitable for the implant lithography because of the plasma induced substrate
damage, developable bottom anti-reflective coating (DBARC) is now the most promising solution to eliminate wafer
topography effects for the implant layer lithography. Currently, some challenges still remain to be solved and DBARC is
not ready for mass production yet. In this study, a novel method is proposed to improve wafer topography effects by use
of sub-resolution features. Compared with DBARC, this new approach is much more cost effective. Numerical study by
use of Sentaurus-Litho simulation tool shows that the new method is promising and deserves more comprehensive
investigation.
As the integration density of VLSI device increases, the overlay accuracy in the photolithography becomes more and more important. In the sub-quarter micron technology, the registration budget is less than 70 nm. Registration error can be induced by the repeatability error of alignment sensor, mask fabrication error, tool induced shift, process induced shift, and so on. One of these misregistration error sources, overlay parameter difference between DI and FI, can cause significant damage to the device because, in most cases, overlay accuracy is checked only in the mask step. In this paper, we studied the relationship of the Edge Detection Algorithm (EDA) and the overlay mark structure to the wafer scale difference.
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