Mr. Sathish Veeraraghavan Profile

Sathish Veeraraghavan

Applications Development Engineer 2 at KLA Tencor Corp

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Author

Publications (11)

Proceedings Article | 19 March 2015 Paper

Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes

Joel Peterson, Gary Rusk, Sathish Veeraraghavan, Kevin Huang, Telly Koffas, Peter Kimani, Jaydeep Sinha

Proceedings Volume 9424, 94240N (2015) https://doi.org/10.1117/12.2086525

KEYWORDS: Semiconducting wafers, Overlay metrology, Lithography, Optical lithography, Scanners, Semiconductors, Photomasks, Dielectrophoresis, Process control, Data modeling

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Proceedings Article | 19 March 2015 Paper

Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices

Honggoo Lee, Jongsu Lee, Sang Min Kim, Changhwan Lee, Sangjun Han, Myoungsoo Kim, Wontaik Kwon, Sung-Ki Park, Pradeep Vukkadala, Amartya Awasthi, J. Kim, Sathish Veeraraghavan, DongSub Choi, Kevin Huang, Prasanna Dighe, Cheouljung Lee, Jungho Byeon, Soham Dey, Jaydeep Sinha

Proceedings Volume 9424, 94240M (2015) https://doi.org/10.1117/12.2085862

KEYWORDS: Semiconducting wafers, Overlay metrology, Lithography, Scanners, Distortion, Plasma enhanced chemical vapor deposition, Semiconductors, Process control, Manufacturing, Error analysis

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Aggressive advancements in semiconductor technology have resulted in integrated chip (IC) manufacturing capability at sub-20nm half-pitch nodes. With this, lithography overlay error budgets are becoming increasingly stringent. The delay in EUV lithography readiness for high volume manufacturing (HVM) and the need for multiple-patterning lithography with 193i technology has further amplified the overlay issue. Thus there exists a need for technologies that can improve overlay errors in HVM. The traditional method for reducing overlay errors predominantly focused on improving lithography scanner printability performance. However, processes outside of the lithography sector known as processinduced overlay errors can contribute significantly to the total overlay at the current requirements. Monitoring and characterizing process-induced overlay has become critical for advanced node patterning. Recently a relatively new technique for overlay control that uses high-resolution wafer geometry measurements has gained significance. In this work we present the implementation of this technique in an IC fabrication environment to monitor wafer geometry changes induced across several points in the process flow, of multiple product layers with critical overlay performance requirement. Several production wafer lots were measured and analyzed on a patterned wafer geometry tool. Changes induced in wafer geometry as a result of wafer processing were related to down-stream overlay error contribution using the analytical in-plane distortion (IPD) calculation model. Through this segmentation, process steps that are major contributors to down-stream overlay were identified. Subsequent process optimization was then isolated to those process steps where maximum benefit might be realized. Root-cause for the within-wafer, wafer-to-wafer, tool-to-tool, and station-to-station variations observed were further investigated using local shape curvature changes – which is directly related to stresses induced by wafer processing. In multiple instances it was possible to adjust process parameters such as gas flow rate, machine power, etc., and reduce non-uniform stresses in the wafer. Estimates of process-induced overlay errors were also used to perform feedforward overlay corrections for 3D-NAND production wafers. Results from the studies performed in an advanced semiconductor fabrication line are reported in this paper.

Proceedings Article | 19 March 2015 Paper

Improvement of depth of focus control using wafer geometry

Honggoo Lee, Jongsu Lee, Sangmin Kim, Changhwan Lee, Sangjun Han, Myoungsoo Kim, Wontaik Kwon, Sung-Ki Park, Sathish Veeraraghavan, JH Kim, Amartya Awasthi, Jungho Byeon, Dieter Mueller, Jaydeep Sinha

Proceedings Volume 9424, 942428 (2015) https://doi.org/10.1117/12.2085848

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Metrology, Scanners, Lithography, Chemical mechanical planarization, Optical lithography, Semiconductors, Etching, Neodymium

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Proceedings Article | 2 April 2014 Paper

Monitoring process-induced overlay errors through high-resolution wafer geometry measurements

K. Turner, P. Vukkadala, S. Veeraraghavan, J. Sinha

Proceedings Volume 9050, 905013 (2014) https://doi.org/10.1117/12.2046340

KEYWORDS: Semiconducting wafers, Overlay metrology, Optical lithography, Mechanics, Shape analysis, Etching, Finite element methods, Scanners, Thin films, Metrology

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Proceedings Article | 31 March 2014 Paper

Characterization and mitigation of overlay error on silicon wafers with nonuniform stress

T. Brunner, V. Menon, C. Wong, N. Felix, M. Pike, O. Gluschenkov, M. Belyansky, P. Vukkadala, S. Veeraraghavan, S. Klein, C. H. Hoo, J. Sinha

Proceedings Volume 9052, 90520U (2014) https://doi.org/10.1117/12.2045715

KEYWORDS: Semiconducting wafers, Overlay metrology, Electronic support measures, Distortion, Optical alignment, Metrology, Photomasks, Lithography, Silicon, Laser range finders

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SPIE Journal Paper | 25 October 2013 Open Access

Characterization of wafer geometry and overlay error on silicon wafers with nonuniform stress

Timothy Brunner, Vinayan Menon, Cheuk Wong, Oleg Gluschenkov, Michael Belyansky, Nelson Felix, Christopher Ausschnitt, Pradeep Vukkadala, Sathish Veeraraghavan, Jaydeep Sinha

JM3, Vol. 12, Issue 04, 043002, (October 2013) https://doi.org/10.1117/12.10.1117/1.JMM.12.4.043002

KEYWORDS: Semiconducting wafers, Electronic support measures, Overlay metrology, Optical alignment, Silicon, Photomasks, Lithography, Laser range finders, Scanners, Metrology

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SPIE Journal Paper | 21 March 2012

Relationship between localized wafer shape changes induced by residual stress and overlay errors

Kevin Turner, Sathish Veeraraghavan, Jaydeep Sinha

JM3, Vol. 11, Issue 1, 013001, (March 2012) https://doi.org/10.1117/12.10.1117/1.JMM.11.1.013001

KEYWORDS: Semiconducting wafers, Distortion, Overlay metrology, Lithography, Optical lithography, Scanners, Thin films, Finite element methods, Thin film deposition, Error analysis

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Proceedings Article | 20 April 2011 Paper

Simulation of non-uniform wafer geometry and thin film residual stress on overlay errors

Sathish Veeraraghaven, Kevin Turner, Jaydeep Sinha

Proceedings Volume 7971, 79711U (2011) https://doi.org/10.1117/12.879493

KEYWORDS: Semiconducting wafers, Overlay metrology, Thin films, Lithography, Optical lithography, Mechanics, Error analysis, Semiconductor manufacturing, Metrology, Edge roughness

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SPIE Journal Paper | 1 October 2009

Predicting distortions and overlay errors due to wafer deformation during chucking on lithography scanners

Kevin Turner, Sathish Veeraraghavan, Jaydeep Sinha

JM3, Vol. 8, Issue 04, 043015, (October 2009) https://doi.org/10.1117/12.10.1117/1.3247857

KEYWORDS: Semiconducting wafers, Optical lithography, Lithography, Overlay metrology, Scanners, Shape analysis, Data modeling, Finite element methods, Error analysis, Chemical elements

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Proceedings Article | 16 November 2007 Paper

Techniques to measure force uniformity of electrostatic chucks for EUV mask clamping

Sathish Veeraraghavan, Jaewoong Sohn, Kevin Turner

Proceedings Volume 6730, 67305G (2007) https://doi.org/10.1117/12.746843

KEYWORDS: Semiconducting wafers, Photomasks, 3D modeling, Extreme ultraviolet lithography, Distortion, Finite element methods, Dielectrics, Silicon, Particles, Interfaces

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Proceedings Article | 20 October 2006 Paper

Measuring force uniformity in electrostatic chucking of EUVL masks

Jaewoong Sohn, Sathish Veerarghavan, Kevin Turner, Roxann Engelstad, Chris Van Peski

Proceedings Volume 6349, 63493B (2006) https://doi.org/10.1117/12.686282

KEYWORDS: Semiconducting wafers, Extreme ultraviolet lithography, Photomasks, Particles, Analytical research, Dielectrics, Interferometry, Data modeling, Finite element methods, Fourier transforms

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Showing 5 of 11 publications

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