In many semiconductor markets, the largest fraction of total lithography cost is photomask cost; therefore any improvements in that area can have a noticeable impact on net chip cost. A significant yield loss mechanism for advanced photomasks is through nonrepairable defects. Providing improved methods to repair defects allows for improvements in mask yield and, therefore, the cost to make a defect-free mask and eventually the cost to produce the integrated circuit. However, the connection between mask yield and integrated circuit price is not a first-order relationship because it bridges between the mask supplier and end-user. SEMATECH and other worldwide consortia have, in the past, bridged this gap by sponsoring programs to develop improved mask infrastructure tools. A significant investment has been made in mask repair tool technology, but the quantitative benefit and return on investment has not been summarized until now. This paper attempts to show the strong benefits to the photomask and semiconductor industries from improving mask repair.
Over the last decade SEMATECH has provided significant guidance in predicting mask costs and their potential
effects on the cost of manufacturing semiconductors. Additionally, these projections have been used to
appropriately fund activities that could have the most impact on reducing mask costs, improving quality and cycle
time. The most recent cost projections provide a comprehensive look at the impact of improvements to the mask
fabrication process. We will provide projections that clearly indicate that appropriately funded mask technologies
can have a significant impact on manufacturing yields and hence, cost and cycle time.
While historical mask cost projections were realistic, the new projections represent the best estimates for mask costs
over the next several years based on the current mask technology and processes1. These projections are significantly
more optimistic than previous estimates. These changes are due primarily to the introduction of new mask repair
technologies, improvements in focused ion beam (FIB), nano-machining and femto-second laser repair.
Microelectronics industry leaders routinely name mask cost and cycle time as top issues of concern. In 2002, a
survey was created with support from SEMATECH and administered by SEMI North America to gather information
about the mask industry as an objective assessment of its overall condition. The survey is designed with the input of
mask technologists from semiconductor manufacturers, merchant mask suppliers, and makers of mask equipment.
The 2005 survey was the fourth in the current series of annual surveys. The survey data can be used as a baseline for
the mask industry and the microelectronics industry to gain a perspective on the technical and business status of the
mask industry. The results may be used to guide future investments on critical path issues. Questions are grouped
into categories: general business profile information, data processing, yields and yield loss mechanisms, delivery
times, returns and services, operating cost factors, and equipment utilization. Because the questions covering
operating cost factors and equipment utilization were just added to the survey, no trend analysis is possible. Within
each category are many questions that together create a detailed profile of both the business and technical status of
the mask industry. The assessment participation has changed from year to year. The 2005 survey, for example,
includes inputs from eight major global merchant and captive mask manufacturers whose revenue represents
approximately 85% of the global mask market.
The extension of optical projection lithography through immersion to patterning features with half pitch ⩽65 nm is placing greater demands on the mask. Strong resolution enhancement techniques (RETs), such as embedded and alternating phase shift masks and complex model-based optical proximity correction, are required to compensate for diffraction and limited depth of focus (DOF). To fabricate these masks, many new or upgraded tools are required to write patterns, measure feature sizes and placement, inspect for defects, review defect printability and repair defects on these masks. Beyond the significant technical challenges, suppliers of mask fabrication equipment face the challenge of being profitable in the small market for mask equipment while encountering significant R&D expenses to bring new generations of mask fabrication equipment to market.
The total available market for patterned masks is estimated to be $2.5B to $2.9B per year. The patterned mask market is about 20% of the market size for lithography equipment and materials. The total available market for mask-making equipment is estimated to be about $800M per year. The largest R&D affordability issue arises for the makers of equipment for fabricating masks where total available sales are typically less than ten units per year. SEMATECH has used discounted cash flow models to predict the affordable R&D while maintaining industry accepted internal rates of return. The results have been compared to estimates of the total R&D cost to bring a new generation of mask equipment to market for various types of tools. The analysis revealed that affordability of the required R&D is a significant problem for many suppliers of mask-making equipment.
Consortia such as SEMATECH and Selete have played an important role in cost sharing selected mask equipment and material development projects. Governments in the United States, in Europe and in Japan have also helped equipment suppliers with support for R&D. This paper summarizes the challenging business model for mask equipment suppliers and highlight government support for mask equipment and materials development.
Microelectronics industry leaders routinely name mask cost and cycle time as top issues of concern. A survey was created with support from International SEMATECH (ISMT) and administered by SEMI North America to gather information about the mask industry as an objective assessment of its overall condition. The survey is designed with the input of mask technologists from semiconductor manufacturers, merchant mask suppliers, and makers of equipment for mask fabrication. This year's assessment is the fourth in the current series of annual reports and is intended to be used as a baseline for the mask industry and the microelectronics industry to gain a perspective on the technical and business status of the mask industry. This report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry. The results may be used to guide future investments on critical path issues. This year's survey contains all of the 2004 survey questions to provide an ongoing database. Additional questions were added to the survey covering operating cost factors and equipment utilization. Questions are grouped into categories: general business profile information, data processing, yields and yield loss mechanisms, delivery times, returns and services, operating cost factors and equipment utilization. Within each category are a many questions that create a detailed profile of both the business and technical status of the mask industry. This assessment includes inputs from eight major global merchant and captive mask manufacturers whose revenue represents approximately 85% of the global mask market. This participation rate is reduced by one captive from 2004. Note: Toppan, DuPont Photomasks Inc and AMTC (new) were consolidated into one input therefore the 2004 and 2005 surveys are basically equivalent.
Polarization dependent diffraction efficiencies in transmission through gratings on specially designed masks with pitch comparable to the wavelength were measured using an angle-resolved scatterometry apparatus with a 193 nm excimer source. Four masks - two binary, one alternating and one attenuated phase shift mask - were included in the experimental measurements. The validity of models used in present commercially available simulation packages and additional polarization effects were evaluated against the experimental scattering efficiencies.
Nanoimprint lithography is a contact-lithography technology invented in 1996 as a low-cost alternative to photolithography for researchers who need high resolution patterning. Initially perceived as a trailing-edge technology for low-cost device fabrication, it has been recently demonstrated to achieve sub-10 nm resolution and alignment, which equal or surpass even the most advanced photolithography today. At Hewlett-Packard, we have successfully used it to fabricate switchable molecular memory arrays with a dimension of 65 nm half pitch. Nanoimprint has been placed on the International Technology Roadmap for Semiconductors (ITRS) as a candidate for next-generation lithography (NGL) for insertion in the 32 nm node in Y2013. The switch from using light to using contact to pattern will indeed bring new challenges, the most important of which are alignment and the 1x mask/template. For alignment, one imprint tool maker has achieved alignment of +/-7 nm 3 sigma using Moire patterns. For template fabrication, the lack of OPC and other sub-resolution features produced large savings in patterning, but it is nearly cancelled out by the need for more aggressive inspection because of the smaller tolerable defect size. The two combined to make the predicted cost of nanoimprint template to be similar to photomasks for 45-nm half pitch. At 32-nm half pitch, EUVL masks do not have complicated sub-resolution features and are predicted to be cheaper than comparable nanoimprint templates provided that the former’s defect levels can be reduced to what is required for economical manufacturing. In both cases, the challenges are not insurmountable and solutions are being actively pursued. However, if nanoimprint is indeed the disruptive technology to photolithography, it needs to take its initial aim at the low-end market rather than mount a frontal challenge at semiconductor manufacturing, which is the high-margin customers that photolithography will pursue and protect at all cost. The recent development in nanotechnology will lead to the commercialization of a new class of nanoscale devices requiring a high-resolution lithographic technique that does not have all the functionalities of photolithography. This approach will provide an initial customer base for nanoimprint to develop and improve and position it to challenge photolithography in the distant future.
Chrome-based absorbers have been the mainstay of the photomask industry for three decades. While chrome is attractive because of its durability and opacity, it conversely poses challenges for etch and repair. Due to large capital investments, any new absorber must be designed to work with existing scanners, mask writers, and mask inspection tools. Furthermore changing absorber materials may not improve defect control in mask blank fabrication, which is a paramount concern in blank fabrication. Consequently, blank manufacturers are reluctant to change from chrome. In terms of return on investment (ROI), the only driver to switch technologies is achieving higher mask and wafer yields. This is a reasonable assumption as both etch and repair tool suppliers believe a non-chrome material like tantalum (Ta) compounds would significantly improve their capabilities with known technologies. A high level estimate shows that with even aggressive improvement assumptions, a 100% conversion from chrome does not save money. Based on the current International SEMATECH (ISMT) cost of ownership (COO) model and improved yields for critical dimension (CD) and defects, a case can be made for converting at and below 100 nm ground rules. An industry wide conversion from chrome to a non-chrome absorber is estimated to cost $100M. By contrast, blank suppliers are reportedly spending "multiple" millions of dollars to improve chrome per year. A widespread concern is whether binary optical masks have enough life left to provide sufficient ROI. Optical lithography will continue to be of use in the foreseeable future. Even as leading-edge production moves to new technology, the main manufacturing volumes will continue to create significant demand for masks for 100 nm to 45 nm for many years. With the industry currently pushing extreme ultraviolet lithography (EUVL), the best situation would be for EUVL and optical lithography to choose the same absorber material. This creates a winning situation for the industry independent of EUVL implementation timing. Today Ta-based films are a reasonable choice.
Defect printability and inspection studies were conducted on a programmed EUV defect mask. The mask was fabricated using Ta-based absorber stack on a Mo/Si multilayer coated 6025 plate. The defect pattern contains a variety of types of defects. The defect printing was performed on the Engineering Test Stand (ETS), which is the 0.1 NA EUV scanner at Sandia National Laboratories in Livermore, CA. The result showed that the printability of defects depended on the defect type and that either notches in or protrusions from absorber lines were the first to print. The minimum printable defect size was approximately 15 nm (1X). Defect inspection was performed on a 257-nm wavelength mask inspection system in die-to-die mode. Seventy-eight out of 120 programmed defects were detected when using 50% detection sensitivity. Maximum detection sensitivity was also tried. However, the number of defects is overwhelmed by the nuisance defects. The minimum defect detected was 52 nm in width. Simulations with a 2-D scalar model are used to verify the results.
Microelectronics industry leaders routinely name mask cost and cycle time as top issues of concern. A survey was created with support from International SEMATECH (ISMT) and administered by SEMI North America to gather information about the mask industry as an objective assessment of its overall condition. The survey is designed with the input of mask technologists from semiconductor manufacturers, merchant mask suppliers, and makers of equipment for mask fabrication. This year's assessment is the third in the current series of annual reports and is intended to be used as a baseline for the mask industry and the microelectronics industry to gain a perspective on the technical and business status of the mask industry. This report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry. The results may be used to guide future investments on critical path issues. This year's survey builds upon the 2003 survey to provide an ongoing database using the same questions as a baseline with only a few minor changes or additions. Questions are grouped into categories: general business profile information, data processing, yields and yield loss mechanisms, delivery times, returns and services. Within each category are a many questions that create a detailed profile of both the business and technical status of the mask industry. This assessment includes inputs from ten major global merchant and captive mask manufacturers whose revenue represents approximately 85% of the global mask market.
Many technological challenges exist for the timely introduction of successive generations of integrated circuits with decreasing feature size. Lithography at dimensions commensurate with those described in the International Roadmap for Semiconductors at technology nodes with half pitch ≤45nm will require complex masks for 193nm immersion or EUV masks. ISMT has a five-year alliance with the State University of New York at Albany to develop EUV mask blanks and EUV resist. A process line to develop low defect extreme ultraviolet (EUV) mask blank multilayers is operational. ISMT is also working with commercial suppliers, who are fabricating EUV mask substrates and multilayer-coated mask blanks. Tools and processes for fabricating, inspecting, reviewing defects and repairing defects for EUV mask blanks are being developed as well. In addition, standards for EUV mask blank requirements and strategies for maintaining defect free EUV masks are being investigated.
To evaluate the ability to achieve the CD control requirements listed in the International Technology Roadmap for Semiconductors (ITRS) and to set error budget targets for focus, dose, PEB temperature uniformity, and mask CD control, statistical lithography simulation was used. A statistical model of total CD control, including the effects of intrafield and interfield error sources, was developed. The exposure tool settings such as wavelength, NA and partial coherence, focus and dose error budgets, lens aberration levels, mask type and pattern pitch values were determined for each node. Monte Carlo simulation was used to predict the CD error due to intrafield dose and focus errors. The contribution to CD error due to the mask was determined using mask CD control values in the ITRS and a calculated MEEF value at various defocus settings. The contribution to CD error due to PEB temperature variations, across wafer dose variations, and variation of aberrations and flare within the exposure field was also simulated. To meet ITRS CD control targets for 130-nm and 90-nm nodes, an alternating PSM mask is required along with a larger CD printed in resist than indicated in the ITRS. Meeting ITRS CD control requirements for 65-nm node and beyond not possible using assumptions detailed here, even with a near ideal APSM. The simulations predicted that if a relaxed pitch and a larger CD in resist were used at the 32nm node, 193nm immersion lithography in combination with a nearly ideal alternating PSM might provide CD control that is comparable to that obtainable using extreme ultraviolet lithography (EUVL).
Phase Shift Masks (PSM) for Extreme Ultraviolet Lithography (EUVL) have the potential for extending the lithographic capability of EUVL beyond the 32-nm node. The concept of EUV PSM structures can be implemented either by adding absorber structures on top of the Mo/Si multilayers (additive approach) or by partial etching into the multilayers (subtractive approach). Among many technical challenges, evaluating optical constants of absorber materials is the most important issue particularly for PSM by the additive approach (PSM-ADD), while the etch stop capability and the etch selectivity with vertical sidewall profile are the main technical challenges for PSM fabricated by the subtractive method (PSM-SUB). For fast turn around of PSM development, the indirect optical constant evaluation through material analysis is a useful metrology technique. The optical constant of TaSiN extracted from Rutherford Backscattering Spectroscopy (RBS) data agrees well with that obtained from the direct measurement by transmission interferometric technique. For PSM-SUB, the concept of embedding B4C and NiFe etch stop layer (ESL) is verified by measuring reflectivity of the ESL embedded substrates and demonstrating good etch stop capability.
We have exposed 10 wafers on the Engineering Test Stand (ETS), the 0.1 NA EUV scanner at Sandia National Laboratories in Livermore, CA. The EUV reflective mask was fabricated in-house using a Ta-based absorber stack on Mo/Si multilayers. The printed wafers contained different line sizes and pitches, line-end shortening measurement structures, contact holes, and patterns for estimating absorber defect printability. The depths of focus of each feature are typically 2 um due to the small NA of the scanner, and these should decrease by at least a factor of 6.25 as the NA's increase to 0.25. The data from measurements of line size through pitch and line-end shortening test structures indicate that both 1D and 2D optical proximity correction will be required. Defects that are either notches in or protrusions from absorber lines are the first to print, and they begin to print when they reach approximately 15~nm (1X) in size. This size threshold is in accordance with the 2003 ITRS specifications. We also report the first printing of SRAM bitcells with EUV lithography.
Conventional lithography techniques have been losing their ability to easily support continuous shrinking of feature sizes, especially when the pattern half-pitch is <60 nm. EUV lithography is one of the leading contenders to replace these conventional techniques. Because the EUV mask structure is many times thicker than the illumination wavelength, scalar Fraunhofer diffraction calculations cannot describe the scattering of light from the EUV masks with enough accuracy. In this paper, we present a rigorous 3-D electromagnetic field simulator for EUV masks. The simulator is based on a 3-D waveguide method developed to calculate the characteristics of the light scattered from nonplanar EUV masks. A typical EUV mask contains as many as 80 reflective layers in addition to the absorbing layers, and we have developed a fast method to calculate the scattering matrix of the reflective layers. Also, based on the existing numerical techniques, we can describe the light scattering in the absorbing layers with complex index of refraction. The simulator has been recently modified to handle oblique illumination conditions, and this is the focus of our paper. Aerial images are calculated in the image plane of a typical EUV stepper, and a threshold resist model is used to predict the printed pattern size. We will first compare our work with published results on dense and isolated lines. Then, we will describe the results of our calculations for two-dimensional patterns (e.g., contacts and islands) under oblique illumination. The typical simulation time is less than 10 hours on a desktop workstation for two-dimensional patterns.
Phase Shift Masks (PSM) for Extreme Ultraviolet Lithography (EUVL) have the potential for extending the lithographic capability of EUVL beyond the 45-nm node. Typical PSM structures, such as for attenuated PSMs (Att-PSMs), are similar to those of binary masks in the sense that patterned structures of one or more layers of absorber (attenuator) are constructed on the EUV multilayer mirror to provide the correct amount of attenuation and phase shift. However, another type of PSM implemented by etching into the Mo/Si multilayers, rather than by adding lithographic structures on top of the Mo/Si multilayers (additive approach) can provide the required phase shift for both attenuated and hard PSMs. One of anticipated technical challenges, i.e. terminating ethcing at a specific depth with good surface uniformity can be sovled by employing an etch stop layer (ESL) embedded at a target depth inside the multilayer. In designing PSMs using this subtractive fabrication technique, the position and thickness of the ESL should be optimized, so that optical function of the multilayer substrate with embedded ESL should be same or close to when it does not have any embedded layer. According to simulation, the print bias for PSMs by etching into the multilayer stack to create the phase shift is smallest and near ideal compared to other types of PSMs or binary masks fabricated by conventional methods. The increase of depth of focus by 25-75% for contacts using an attenuated PSM and by 50-100% for lines using an ideal har dPSM is another lithographic advantage as well. The design and method of fabricating PSMs by etchign intothe multilayers is described, which include the optimziation of the thinkness and dpeth of the embedded layer. Experimental results of the multilayer etch process demonstrate initial feasibility of the subtractive approach to fabricating EUV PSMs.
EUV lithography at 13nm wavelengths will require the use of reflective multi-layer mask substrates with a patterned absorbing top layer. As the height of the absorber is many times the wavelength of the exposure radiation, EUV masks are true topographical entities. Therefore, scalar Frauenhofer diffraction simulations are not completely valid and accurate. Rigorous solution of Maxwell's equations in the topography is necessary to accurately predict many of the lithographic effects of these masks. Additionally, the interactions of the non-vertical radiation reflectance from the multilayer stack with the absorber causes further non-intuitive lithographic results which need to be understood and optimized. To further the rigorous understanding of EUV mask effects, we have extended existing 2D and 3D rigorous simulators to model EUV lithography diffraction. These simulators, METRO and METROPOLE-3D respectively, use the waveguide method for fast and accurate computation of topographical mask structures. Modifications of these simulators enable an order of magnitude speedup in the calculation of results containing large numbers of EUV multilayers, improve mask dimension modeling accuracy and enable accurate modeling of the non-normal EUV source illumination through a range of pitch values. Rigorous illumination and multilayer defect analysis results will also be shown. Additional comparisons to recently published rigorous EUV simulations results and impressive runtime results on standard desktop workstations are presented. The results show that for EUV lithography the best focus position and the symmetry of the aerial image intensity profile with respect to best focus is affected by the pattern pitch.
We have demonstrated the fabrication of working 130 nm-node SRAMs with high yield using single layer ultra-thin resist (UTR) integrations. Transistor gates were fabricated using 140-nm-thick resist films in combination with a single layer, inorganic anti-reflective coating (ARC) that also acted as a hardmask (HM). An aggressive ARC/HM removal process was developed to enable the use of a thick ARC/HM. The thick ARC/HM was necessary to allow the incorporation of a resist trim step prior to polysilicon gate etch that reduced the transistor gate lengths in silicon from the printed critical dimension (CD) in resist. Transistor performance for both NMOS and PMOS devices with UTR-fabricated gates was equivalent to the performance of standard transistors. Working SRAM arrays were fabricated using UTR at the gate layer that achieved natural yield within 10% of the yield achieved with a thick resist process, and in some cases, with yield that exceeded the thick resist process. CD control for the UTR gate photo process was equivalent to the baseline photo process, and the UTR gate photo process was optimized to increase device yield. Contacts fabricated using 120-nm-thick resist films exhibited electrical characteristics equivalent to those fabricated with standard processes, and yielding SRAM devices were fabricated using UTR at the contact layer. Defect inspection of UTR contact patterning detected the formation of pinholes in the UTR films; however, the formation of pinholes was found to be dependent upon substrate-resist interactions.
Phase defects in extreme UV lithography masks made from Mo/Si multilayer thin films can be removed by heating the metal multilayer to produce a localized phase transition. The experimental situation has been simulated using a Monte Carlo method to determine the deposition of energy from the incident electrons, and the resultant elevation of temperature has been found by solving the thermal diffusion equation. The effects of operating parameters such as beam energy, beam current, and beam spot size have been investigated. It is shown that the effect of surface radiation cooling is negligible, and that only a steady state solution needs to be considered.
Low-k1 imaging, high-NA optics, pattern collapse, and the absorption of resist materials in 157-nm and EUV lithographies are driving down the thickness of the photoresist layer in integrated circuit fabrication processes. Although devices and test structures have been successfully fabricated with resist films thinner than 160 nm on various levels, the fabrication of working devices with high yield using ultrathin resist (UTR) integrations on multiple device layers has yet to be demonstrated. In the present work, gates have been patterned with 140-nm thick resist films with 10-15 defects per wafer, none of which are specific to the UTR process. Similar UTR gates were also patterned over 80-nm steps with no defects associated with the topography. The UTR NMOS transistors in this work have 10 pA/micrometers leakage and 400 (mu) A/micrometers drive currents, but the PMOS transistors do not perform as well. The line-edge roughness (LER) is 5-8 nm 3(sigma) depending upon exposure mask (binary vs. PSM) and substrate. Etching into 100 nm of crystalline Si reduces the LER to 4-7 nm 3(sigma) . The power spectral densities of the roughness have a Lorentzian shape, and most of the roughness occurs over length scales larger than 100 nm. Contact chains with electrical characteristics comparable to standard processes were fabricated with 120-nm thick resist films. Polysilicon as thick as 150 nm was etched successfully with 80-nm thick resist films and hardmasks.
Significant progress has been made in developing mask fabrication processes for extreme ultraviolet lithography (EUVL). The mask blank for EUVL consists of a low thermal expansion material substrate having a square photomask form factor that is coated with Mo/Si multilayers. A SEMI standard is now available for mask substrates. SEMI standards are also being developed for mask mounting, for mask blank multilayers and absorbers and for mask handling and storage. Several commercial suppliers are developing polishing processes for LTEM substrates, and they are progressing toward meeting the requirements for flatness, surface roughness, and defects. Significant progress has been made in developing mask blank multilayer coating processes with low added defect density. Besides lowering added defect density, methods to reduce defect printability are being developed to effectively enable repair of many defect types. Calculations of EUVL mask cost indicate that defect repair processes could increase yield of EUV mask blanks and allow initial defect density targets for mask blanks to be relaxed. The mask patterning process for EUVL is nearly the same as that for conventional binary optical lithography masks. Eight absorbers have been evaluated, and two absorbers-TaN and Cr--will probably meet the requirements after some further development.
EUV mask blanks are fabricated by depositing a reflective Mo/Si multilayer film onto super-polished substrates. Small defects in this thin film coating can significantly alter the reflected field and introduce defects in the printed image. Ideally one would want to produce defect-free mask blanks; however, this may be very difficult to achieve in practice. One practical way to increase the yield of mask blanks is to effectively repair multilayer defects, and to this effect we present two complementary defect repair strategies for use on multilayer-coated EUVL mask blanks. A defect is any area on the mask which causes unwanted variations in EUV dose in the aerial image obtained in a printing tool, and defect repair is correspondingly defined as any strategy that renders a defect unprintable during exposure. The term defect mitigation can be adopted to describe any strategy which renders a critical defect non-critical when printed, and in this regard a non-critical defect is one that does not adversely affect device function. Defects in the patterned absorber layer consist of regions where metal, typically chrome, is unintentionally added or removed from the pattern leading to errors in the reflected field. There currently exists a mature technology based on ion beam milling and ion beam assisted deposition for repairing defects in the absorber layer of transmission lithography masks, and it is reasonable to expect that these this technology will be extended to the repair of absorber defects in EUVL masks . However, techniques designed for the repair of absorber layers can not be directly applied to the repair of defects in the mask blank, and in particular the multilayer film. In this paper we present for the first time a new technique for the repair of amplitude defects as well as recent results on the repair of phase defects.
Attenuated Phase Shift Masks (Att-PSM) have been actively investigated and developed for conventional optical lithography to enhance the lithographic performance. In this paper, Att-PSM for Extreme Ultraviolet Lithography (EUVL) is compared to binary EUVL masks through simulation. Additionally, a new structural design for EUVL Att-PSM that is intended to enhance the image contrast during the inspection is also presented. Aerial image simulation for 50 and 35-nm wide contact holes was performed using an internally developed optical projection lithography simulator. Analysis of phase shift and attenuation for various combinations of Att-PSM layers was also done using an internally developed simulator based on optical multilayer thin film theory. The results of aerial image simulation agree with previously published results in that Att-PSM for EUVL provide steeper edge profile and higher peak intensity compared to the binary EUVL mask. These enhanced aerial images provide greater exposure latitude and 28 percent to 80 percent greater depth of focus for Att-PSM compared to binary masks for printing contacts. The simulations were also used to set initial targets for phase and reflectance control of the PSM stack for 35-nm contacts. Mean reflectance between 3 and 6 percent and phase of 180 +/- 10 degrees result in significantly larger DOF than for binary masks. The prototype structure simulated for an EUVL Att-PSM consists of an upper dielectric layer (SiON) and a lower metal layer (TaN or Cr) on top of Mo/Si multilayer mirror. With this dual layer scheme, satisfying the optical requirements is easier than with a single layer structure because accurate control of phase shift and attenuation is possible by controlling the thickness of both the upper and lower layers. Obtaining the desired phase shift and transmission using a single layer is difficult. The advantage of having a dielectric (SiON) top layer is that the thickness of dielectric layer can be optimized to enhance the image contrast at inspection wavelength (normally DUV) as well as to provide the desired phase shift at exposure wavelength (13.4-13.5nm). Another advantage of Att-PSM for EUVL is the reduced height of patterned structure on the multilayer mirror which provides a relative advantage in resolution by reducing the image blur caused by the shadowing effects of the taller absorber stack.
This paper presents the results of patterned and unpatterned EUV mask inspections. We will show inspection results related to EUV patterned mask design factors that affect inspection tool sensitivity, in particular, EUV absorber material reflectivity, and EUV buffer layer thickness. We have used a DUV (257nm) inspection system to inspect patterned reticles, and have achieved defect size sensitivities on patterned reticles of approximately 80 nm. We have inspected EUV substrates and blanks with a UV (364nm) tool with a 90nm to a 120 nm PSL sensitivity, respectively, and found that defect density varies markedly, by factors of 10 and more, from sample to sample. We are using this information in an ongoing effort to reduce defect densities in substrates and blanks to the low levels that will be needed for EUV lithography. While DUV tools will likely meet the patterned inspection requirements of the 70 nm node in terms of reticle defect sensitivity, wavelengths shorter than 200 nm will be required to meet the 50 nm node requirements. This research was sponsored in part by NIST-ATP under KLA-Tencor Cooperative Agreement #70NANB8H44024.
Development of manufacturing infrastructure is required to ensure a commercial source of mask substrates for the timely introduction of EUVL. Improvements to the low thermal expansion materials that compose the substrate have been made, but need to be scaled to production quantities. We have been evaluating three challenging substrate characteristics to determine the state of the infrastructure for the finishing of substrates. First, surface roughness is on track and little risk is associated with achieving the roughness requirement as an independent specification. Second, with new flatness-measuring equipment just coming on line, the vendors are poised for improvement toward the SEMI P37 flatness specification. Third, significant acceleration is needed in the reduction of defect levels on substrates. The lack of high-sensitivity defect metrology at the vendors' sites is limiting progress in developing substrates for EUVL.
To meet critical dimension control error budgets for extreme UV lithography (EUVL) tools, the reflectivity bandpass of multilayers on the mask must be well matched to the bandpass of the optical system in the exposure tool. The reflectivity bandpass and peak reflectivity of the mask multilayers must also be highly uniform to minimize illumination uniformity errors in the exposure tool Calculations were performed to determine the required mask multilayer matching to exposure tool optics. Calculated ideal reflectivity curves and measured reflectivity versus wavelength values for typical masks made with ion beam sputtering and for the coating on the optics for the ETS were used. The impact on the mask coating requirements when using more than 6 multilayer- coated optics in production exposure tools was also quantified. To meet error budgets established for the ETS, the mask multilayer coating centroid wavelength at all points in the image field should be 13.334 +/- 0.040 nm, and peak reflectivity must be uniform to within +/- 0.5 percent absolute. A roadmap is proposed for mask multilayer reflectivity requirements for future industry roadmap nodes.
Detailed thermal expansion measurements and internal homogeneity measurements of the glass-ceramic material Zerodur were undertaken to examine its usefulness for EUVL. Repeat measurements on 100-mm long samples from three castings exhibit an expansion of approximately 12 +/- 2 ppb/K 2 (sigma) in the temperature range of interest for EUVL, corresponding to Class C of the draft SEMI 3148 standard. Internal homogeneity measurements reveal extremely small refractive index variations, suggesting comparably small compositional variations. This in turn is viewed as a necessary but not sufficient condition for high CTE uniformity, a factor required by EUVL applications.
Optical projection lithography has been the principal vehicle of semiconductor manufacturing for more than 20 years and is marching aggressively to satisfy the needs of semiconductor manufacturers for 100nm devices. However, the complexity of optical lithography continues to increase as wavelength reduction continues to 157nm. Extreme Ultraviolet Lithography (EUVL), with wavelength from 13-14 nm, is evolving as a leading next generation lithography option for semiconductor industry to stay on the path laid by Moore's Law. Masks are a critical part of the success of any technology and are considered to be high risk both for optical lithography and NGL technologies for sub-100nm lithography. Two key areas of EUV mask fabrication are reflective multilayer deposition and absorber patterning. In the case of reflective multilayers, delivering defect free multilayers for mask blanks is the biggest challenge. Defect mitigation is being explored as a possible option to smooth the multilayer defects in addition to optimization of the deposition process to reduce defect density. The mask patterning process needs focus on the defect-free absorber stack patterning process, mask cleaning, inspection and repair. In addition, there is considerable effort to understand by simulations, the defect printability, thermal and mechanical distortions, and non-telecentric illumination, to mention a few. To protect the finished mask from defects added during use, a removable pellicle strategy combined with thermophoretic protection during exposure is being developed. Recent migration to square form factor using low thermal expansion material (LTEM) is advantageous as historical developments in optical masks can be applied to EUV mask patterning. This paper addresses recent developments in the EUV mask patterning and highlights critical manufacturing process controls needed to fabricate defect-free full field masks with CD and image placement specifications for sub-70nm node lithography. No technology can be implemented without establishing the commercial infrastructure. The rising cost seems to be a major issue affecting the technology development. With respect to mask fabrication for commercial availability, a virtual mask shop analysis is presented that indicates that the process cost for EUVL masks are comparable to the high end optical mask with a reasonable yield. However, the cost for setting up a new mask facility is considerably high.
Extreme ultraviolet lithography (EUVL), and possibly 157-nm lithography, will require thin imaging layers (< 1500 Angstroms). The leading EUV resist strategy utilizes thin resists based on materials designed for 248 nm wavelength exposure and hardmasks. This process has produced lines and spaces with reasonable linearity, resolution, photospeed, and line-edge roughness. Although previous work has approached these limits, integration of sub-150nm resists and hardmasks into current IC manufacturing process flows with acceptable defect control has not yet been demonstrated. The authors are investigating ultrathin resist processing for the gate and back end levels and have collected data on coating properties, defect density, etch selectivity, exposure latitude, and depth of focus. Key results include the demonstration of etching 1500 Angstroms of poly-Si with a 1200 Angstroms thick photoresist etch mask and the demonstration of via chain yield that is comparable to standard thickness resist processes.
KEYWORDS: Photons, Dielectrics, Monte Carlo methods, Absorption, Electron beam lithography, Projection lithography, Solids, Oxides, Chemical species, CMOS devices
Electron projection lithography (EPL) uses 100keV electrons to minimize the effects of beam blur, minimize forward scattering, and expose high aspect ratio resist patterns. When these electrons undergo collisions in the substrate, they decelerate and emit Bremsstrahlung photons. The Bremsstrahlung photons have a continuum spectrum with high energy, and absorption of these photons might damage device layers already present during the electron lithography step. A simulator that uses a Monte Carlo approach to track electron trajectories in this substrate calculates the Bremsstrahlung spectrum and its spatial distribution. The Bremsstrahlung temporal spectrum and spatial distribution was calculated with a model selected after reviewing various approaches described in the literature. The density of the Bremsstrahlung photons absorbed by the film stack of device layers is then calculated. Bremsstrahlung absorption by thin oxide layers on silicon is small compared to the SiO2 bond density. For gate dielectrics containing high atomic number metals such as HfO2, the absorbed flux of photons generated by the electron exposure is about one order of magnitude larger than for SiO2 gate dielectrics. Because the gate dielectric for future CMOS devices is only a few nanometers in thickness and the pixel exposure time is only a fraction of a millisecond, few of the photons generated by electron exposure are absorbed in the gate dielectric. The effects of absorption in other layers is negligible. The calculated number of charges in the gate dielectric that result from photon absorption is not large enough to shift the flat band voltage by more than ~1 mV. For the cases simulated with this model, electron projection lithography is not expected to cause significant effects on CMOS gate dielectric properties, even for metal oxide dielectrics.
The Engineering Test Stand (ETS) is a developmental lithography tool designed to demonstrate full-field EUV imaging and provide data for commercial-tool development. In the first phase of integration, currently in progress, the ETS is configured using a developmental projection system, while fabrication of an improved projection system proceeds in parallel. The optics in the second projection system have been fabricated to tighter specifications for improved resolution and reduced flare. The projection system is a 4-mirror, 4x-reduction, ring-field design having a numeral aperture of 0.1, which supports 70 nm resolution at a k1 of 0.52. The illuminator produces 13.4 nm radiation from a laser-produced plasma, directs the radiation onto an arc-shaped field of view, and provides an effective fill factor at the pupil plane of 0.7. The ETS is designed for full-field images in step-and-scan mode using vacuum-compatible, magnetically levitated, scanning stages. This paper describes system performance observed during the first phase of integration, including static resist images of 100 nm isolated and dense features.
Substrate or phase defects on EUVL masks are considered non- repairable because they lie underneath or are imbedded in the multi-layer mirror. One defect specification requires that no more than three defects greater than 80nm can be present on a starting substrate. Finding and removing these small defects before multi-layer deposition can be very difficult tasks. It has been shown that very small defects can have an influence on the patterned absorber stack and the printed image from an EUVL system. Substrate defect mitigation using TaSiN smoothing layers has been investigated. Programmed Cr defects were formed using standard semiconductor processing techniques and subsequently buried by the defect mitigating film. Experimental results are presented showing that a sputtering process can be used to deposit very smooth and thick TaSiN films (i.e. less than 0.2-nm RMS surface roughness and greater than 1.5-microns thick) as a substrate defect mitigation layer.
The three-layer absorber stack for EUVL reticles currently consists of an absorber, repair buffer and etch stop layers. The repair buffer should exhibit high etch selectivity during the absorber etch processes (i.e. pattern transfer and focused ion beam (FIB) repair), be thermally and electrically conductive, optimally thin and have high etch selectivity to the silicon-capping layer over the Mo/Si multi-layer mirror. The absorber materials that have been studied in the past are TaSiN and Cr with SiON as the repair buffer on top of a Cr etch stop layer. The SiON repair buffer is insulating, exhibiting low thermal and electrical conductivity. Also, the required thickness for FIB repair is greater than 750 Angstroms using a standard 30-keV Ga+ FIB tool, while the etch selectivity to the silicon capping layer during pattern transfer is less than five to one necessitating a Cr etch stop. A sputtered carbon repair buffer exhibiting the required qualities has been studied. The carbon film is thermally and electrically conductive and exhibits extremely high reactive ion etch selectivity to the silicon-capping layer. Carbon also has the lowest sputter yield out of all the elements opening a larger FIB repair process window without using gas-assisted etching. A conductive repair buffer also prevents the possibility of static charge buildup on the mask that could damage patterns during an electrostatic discharge.
With the acceptance of AAPSM’s by most major semiconductor manufacturers, it is necessary to build a significant number of these masks in a cost effective and controlled manner. Optical methods of metrology used for many years in the photomask industry for binary masks are unsuitable for certain metrology applications related to AAPSM manufacture and repair. Recent work performed on a Dimension 9000M-PM automated atomic force microscope shows promise for both process control and defect review applications for AAPSM’s and overcome some of the limitations of optical and SEM based metrologies. AFM metrology is shown to be able to quantify shifter step heights and phase error for features as small as 100 nm. Further, these systems are able to read in defect coordinate maps and automatically drive to these sites and scan. The scanned data provides pixel-by-pixel height data that can be used by repair tools to establish the proper dose for defect ablation.
A UV inspection tool has been used to image and inspect Next Generation Lithography (NGL) reticles. Inspection images and simulations have been used to provide feedback to mask makers so that inspectability of NGL masks can be optimized. SCALPEL masks have high optical contrast and look much the same in reflection as conventional chrome on glass masks do in transmission. EPL stencil masks can be imaged well in reflection, but defects below the top surface, in the cutouts, may not be detectable optically. EUV masks that have been made to date tend to have relatively low contrast, with line edge profiles that are complex due to interference effects. Simulation results show that improved EUV inspection images can be obtained with a low reflectivity absorbing layer and proper choice of buffer layer thickness.
A model has been developed to predict the cost of extreme ultraviolet lithography (EUVL) masks. The mask blank for EUVL consists of a low thermal expansion material substrate having a square photomask form factor and is coated with reflective Mo/Si multilayers. Absorber layers are deposited on the multilayer and patterned. EUVL mask patterning will use evolutionary improvements in mask patterning and repair equipment. One of the challenges in implementing EUVL is to economically fabricate multilayer-coated mask blanks with no printable defects. The model of mask cost assigns yield and time required for each of the steps in fabricating EUVL masks from purchase of a polished substrate to shipment of a patterned mask. Data from present multilayer coating processes and present mask patterning processes are used to estimate the future cost of EUVL masks. Several of the parameters that significantly influence predicted mask cost are discussed in detail. Future cost reduction of mask blanks is expected from learning on substrate fabrication, improvements in low defect multilayer coating to consistently obtain <0.005 defects cm-2, and demonstration of multilayer smoothing which reduces the printability of substrate defects. The model predicts that the price range for EUVL masks in production will be S30-40K, which is comparable to the price of complex phase shift masks needed to use optical lithography for 70 nm critical dimension patterning.
Minimizing image placement errors due to thermal distortion of the mask is a key requirement for qualifying EUV Lithography as a Next Generation Lithography (NGL). Employing Low Thermal Expansion Materials (LTEMs) for mask substrates is a viable solution for controlling mask thermal distortion and is being investigated by a wide array of researchers, tool makers, photomask suppliers, and material manufacturers. Finite element modeling has shown that an EUVL mask with a Coefficient of Thermal Expansion (CTE) of less than 20 ppb/K will meet overlay error budgets for <EQ 70 nm lithography at a throughput of 80 wafers per hour. In this paper, we describe the functional differences between today's photomask and EUVL masks; some of these differences are EUVL specific, while others are natural consequences of the shrinking critical dimension. We demonstrate that a feasible manufacturing pathway exists for Low Thermal Expansion Material (LTEM) EUVL masks by fabricating a wafer-shaped LTEM mask substrate using the same manufacturing steps as for fabricating Si wafers. The LTEM substrate was then coated with Mo/Si multilayers, patterned, and printed using the 10X Microstepper. The images were essentially indistinguishable from those images acquired from masks fabricated from high quality silicon wafers as substrates. Our observations lend further evidence that an LTEM can be used as the EUVL mask substrate material.
In an attempt to narrow the choice for an absorber used in EUV masks, different materials are being evaluated. These materials need to meet the absorber requirements of EUV absorbance, emissivity, inspection, and repair, to name a few. We have fabricated masks using Cr absorbers. The absorber stack consists of a repair buffer of SiON and a conductive etch stop of Cr sandwiched between the SiON repair buffer film and the Mo/Si multilayer mirror deposited on a Si wafer. However, to increase the process latitude, the Cr etch stop needs to be removed from the stack, in particular for mask repair. The absorber layer was patterned using commercial DUV resist and the pattern was transferred using reactive ion etching (RIE) with halogen-based gases. Completed masks exhibited negligible shift in the centroid wavelength of reflectivity and less than 2% loss in peak reflectivity due to mask patterning. Completed masks were exposed at Sandia National Laboratories' 10X EUV exposure system and equal lines and spaces down to 80 nm were successfully printed. The masks were also imaged in a microscope with 248 nm wavelength, and the focused ion beam repair selectivity to the buffer layer (SiON) was established. The paper summarizes the mask fabrication process, EUV printability, mask repair, inspection and emissivity for EUVL masks with Cr absorber.
EUVL mask blanks consist of a distributed Bragg reflector made of 6.7 nm-pitch bi-layers of Mo and Si deposited upon a precision Si or glass substrate. The layer deposition process has been optimized for low defects, by application of a vendor-supplied but highly modified ion-beam sputter deposition system. This system is fully automated using SMIF technology to obtain the lowest possible environmental- and handling-added defect levels. Originally designed to coat 150 mm substrates, it was upgraded in July 1999 to 200 mm and has coated runs of over 50 substrates at a time with median added defects > 100 nm below 0.05/cm2. These improvements have resulted from a number of ion-beam sputter deposition system modifications, upgrades, and operational changes, which will be discussed. Success in defect reduction is highly dependent upon defect detection, characterization, and cross- platform positional registration. We have made significant progress in adapting and extending commercial tools to this purpose, and have identified the surface scanner detection limits for different defect classes, and the signatures of false counts and non-printable scattering anomalies on the mask blank. We will present key results and how they have helped reduce added defects. The physics of defect reduction and mitigation is being investigated by a program on multilayer growth over deliberately placed perturbations (defects) of varying size. This program includes modeling of multilayer growth and modeling of defect printability. We developed a technique for depositing uniformly sized gold spheres on EUVL substrates, and have studied the suppression of the perturbations during multilayer growth under varying conditions. This work is key to determining the lower limit of critical defect size for EUV Lithography. We present key aspects of this work. We will summarize progress in all aspects of EUVL mask blank development, and present detailed results on defect reduction and mask blank performance at EUV wavelengths.
Extreme Ultra-Violet lithography is one of the leading next generation lithography options. Currently, EUV masks are routinely made of reflective mirrors made of Mo/Si multi- layers, which have a peak reflectivity of 67.5% at a wavelength of 13.4 nm. However, in order to increase the throughput of an EUVL system, a new set of Be-based multi- layers are being developed, which have a peak reflectivity of near 70% at 11.4. The two materials that have recently been developed are Mo/Be and MoRu/Be multi-layers. Beryllium based multi-layer masks show great promise for a significant increase in the lithography system throughput (2 - 3X over the current Mo/Si multi-layer mask) due to their increased reflectivity and bandwidth at 11.4 nm where the xenon laser plasma source is more intense. We have successfully developed a process to fabricate masks using Be-based multi-layers. The absorber stack consists of TaSiN (absorber), SiON (repair buffer) and Cr (conductive etch stop) deposited on the multi- layer mirror. Lawrence Livermore National Laboratory supplied the Mo/Be and MoRu/Be multi-layer mirrors used to fabricate the masks. Completed masks were exposed at Sandia National Laboratories' 10X EUV exposure system and equal lines and spaces down to 80 nm were successfully printed. The paper addresses the issues and challenges to fabricate the mask using Be-based multi-layers and a comparison will be made with the Mo/Si multi-layer mask patterning process.
We report on the comparison of defect printability experimental results with at-wavelength defect inspection and printability modeling at extreme ultraviolet (EUV) wavelengths. Two sets of EUV masks were fabricated with nm- scale substrate defect topographies patterned using a sacrificial layer and dry-etch process, while the absorber pattern was defined using a subtractive metal process. One set of masks employed a silicon dioxide film to produce the programmed defects, whereas the other set used chromium films. Line-, proximity- and point-defects were patterned and had lateral dimensions in the range of 0.2 micrometer X 0.2 micrometer to 8.0 micrometer X 1.5 micrometer on the EUV reticle, and a topography in the range of 8 nm - 45 nm. Substrate defect topographies were measured by atomic force microscopy (AFM) before and after deposition of EUV-reflective Mo/Si multilayers. The programmed defect masks were then characterized using an actinic inspection tool. All EUVL printing experiments were performed using Sandia's 10x- reduction EUV Microstepper, which has a projection optics system with a wavefront error less than 1 nm, and a numerical aperture of 0.088. Defect dimensions and exposure conditions were entered into a defect printability model. In this investigation, we compare the simulation predictions with experimental results.
The mask is deemed one of the areas that require significant research and development in EUVL. Silicon wafers will be used for mask substrates for an alpha-class EUVL exposure tool due to their low-defect levels and high quality surface finish. However, silicon has a large coefficient of thermal expansion that leads to unacceptable image distortion due to absorption of EUV light. A low thermal expansion glass or glass-ceramic is likely to be required in order to meet error budgets for the 70 nm node and beyond. Since EUVL masks are used in reflection, they are coated with multilayers prior to patterning. Surface imperfections, such as polishing marks, particles, scratches, or digs, are potential nucleation sites for defects in the multilayer coating, which could result in the printed defects. Therefore we are accelerating developments in the defect reduction and surface finishing of low thermal expansion mask substrates in order to understand long-term issues in controlling printable defects, and to establish the infrastructure for supplying masks. In this paper, we explain the technical requirements for EUVL mask substrates and describe our efforts in establishing a SEMI standard for EUVL masks. We will also report on the early progress of our suppliers in producing low thermal-expansion mask substrates for our development activities.
Lithographic masks must maintain dimensional stability during exposure in a wafer stepper. In extreme UV lithography, multilayer coatings are deposited on a flat mask, substrate to make the mask surface reflective at EUV wavelengths. About 40 percent of the incident EUV radiation is absorbed by the multilayer coatings causing a temperature rise. The choice of mask substrate material affects dimensional stability due to thermal expansion and/or deformation. Finite element modeling has ben used to investigate the proper choice of mask substrate material and to explore the efficacy of various thermal management strategies. This modeling indicates that significant machine design and engineering challenges are necessary in order to employ Si as a mask substrate. Even if these challenges can be met, the thermal expansion of Si is likely to be too large to meet overlay error budgets for lithography at ground rules beyond the 100 nm technology node. ULE - a single phase, fused silica glass doped with titania - has near zero thermal expansion at the temperatures where EUV lithography is performed. Due to its small coefficient of thermal expansion, ULE does not undergo appreciable instantaneous or transient thermal expansion that results in image placement error.
Extreme UV Lithography (EUVL) is one of the leading candidates for the next generation lithography, which will decrease critical feature size to below 100 nm within 5 years. EUVL uses 10-14 nm light as envisioned by the EUV Limited Liability Company, a consortium formed by Intel and supported by Motorola and AMD to perform R and D work at three national laboratories. Much work has already taken place, with the first prototypical cameras operational at 13.4 nm using low energy laser plasma EUV light sources to investigate issues including the source, camera, electro- mechanical and system issues, photoresists, and of course the masks. EUV lithograph masks are fundamentally different than conventional photolithographic masks as they are reflective instead of transmissive. EUV light at 13.4 nm is rapidly absorbed by most materials, thus all light transmission within the EUVL system from source to silicon wafer, including EUV reflected from the mask, is performed by multilayer mirrors in vacuum.
In extreme ultraviolet lithography (EUVL), the technology specific requirements on the mask are a direct consequence of the utilization of radiation in the spectral region between 10 and 15 nm. At these wavelengths, all condensed materials are highly absorbing and efficient radiation transport mandates the use of all-reflective optical systems. Reflectivity is achieved with resonant, wavelength-matched multilayer (ML) coatings on all of the optical surfaces -- including the mask. The EUV mask has a unique architecture -- it consists of a substrate with a highly reflective ML coating (the mask blank) that is subsequently over-coated with a patterned absorber layer (the mask). Particulate contamination on the EUVL mask surface, errors in absorber definition and defects in the ML coating all have the potential to print in the lithographic process. While highly developed technologies exist for repair of the absorber layer, no viable strategy for the repair of ML coating defects has been identified. In this paper the state- of-the-art in ML deposition technology, optical inspection of EUVL mask blank defects and candidate absorber patterning approaches are reviewed.
The printability of defects in x-ray masks was simulated in three dimensions using the CXrL toolset software developed at the University of Wisconsin and resist dissolution software developed in a collaboration between University of California at Berkeley and Motorola. Isolated defects on mask membranes and isolated defects on pellicle membranes mounted behind the mask membrane were modeled. Defects close to x-ray absorber features and absorber fabrication defects were also considered. Spheres and parallelepiped defect shapes composed of PMMA, ammonium sulfate, and stainless steel were modeled at exposure gaps in the range 10 - 50 micrometers. Attenuation of a variety of potential defect materials was calculated for the IBM Advanced Lithography Facility Helios synchrotron source and beam-line x-ray spectrum. The dose-to-clear for 400 and 500 nm thickness APEX-E films was then used to predict what thickness of defect material would result in a printed defect. Image formation model predictions of defect printability in APEX-E resist were compared to attenuation calculations, indicating that defect shape and x-ray phase shift in the defect material has a profound impact on defect printability for materials that are not highly attenuating. Spheres printed more readily than parallelepipeds. Increasing the exposure gap reduced printability slightly. Experiments to determine the printability of organic spheres added to x-ray masks were compared to simulation to verify its accuracy. Based on modeling results, the minimum size of isolated defects on x- ray masks that printed are presented. The minimum size of defects that changed printed line-width were also discussed. Based on these results, defect inspection sensitivity, cleaning capability, and repair resolution for less than or equal to 175 nm line-width x-ray masks can be established.
Electrical linewidth measurements of etched, N+-doped polysilicon submicron lines were carried out to study the effects of dose and gap on exposure latitude in proximity X-ray lithography. Isolated lines and equal line/space pairs having linewidths from 0.15 micrometers to 0.35 micrometers on the X-ray mask were printed in APEX-M resist at gaps ranging from 26 micrometers to 34 micrometers using a Karl Suss stepper. Lithography was carried out at the IBM Advanced Lithography Facility using the Helios 1 synchrotron. Low voltage scanning electron microscopy (SEM) measurements in top-down mode using the linear regression algorithm are compared to electrical linewidth measurements. Reactive-Ion Etch bias is determined by comparing top-down SEM of resist after exposure, on both 50 and 330-nm-thick polysilicon, to top-down SEM after etching. Both resist and etched line profiles are examined in cross section using SEM. The etch bias and the change in line profiles were found to account for most of the offset between the SEM and the electrical linewidth measurements. The results of SEM-measured averaged across the field, were also compared to two-dimensional aerial images (determined using average SEM-measured mask linewidths) and resist dissolution simulations to examine simulation accuracy.
A shared aperture using only reflective optics for two coherent beams with different wavelengths is desired. Beams that share an aperture are colinear, and they have the same transverse phase profile across the aperture as their respective sources. A shared aperture system composed entirely of reflective phase gratings is presented here. Using the Talbot effect that is observed in Fresnel diffraction from periodic objects, the phase of the beams is preserved, and the efficiency of the system is maximized. An experimental Talbot shared aperture system using HeNe and HeCd beams has an efficiency of 88.1% for the HeNe beam and 70.3% for the HeCd beam. These measured efficiencies agree well with computer simulations.
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