As design rule of semiconductor decreases continuously, overlay error control gets more and more important and challenging. It is also true that On Product Overlay (OPO) of leading edge memory device shows unprecedented level of accuracy, owing to the development of precision optics, mechanic stage and alignment system with active compensation method. However, the heating of reticle and lens acts as a dominant detriment against further improvement of overlay. Reticle heating is more critical than lens heating in current advanced scanners because lens heating can be mostly compensated by feed-forward control algorithm. In recent years, the tools and technical ideas for reticle heating control are proposed and thought to reduce the reticle heating effect. Nevertheless, it is not still simple to predict the accurate heating amount and overlay. And it is required to investigate the parameters affecting reticle heating quantitatively. In this paper, the reticle pattern density and exposure dose are considered as the main contributors, and the effects are investigated through experiments. Mask set of various transmittance are prepared by changing pattern density. After exposure with various doses, overlay are measured and analyzed by comparing with reference marks exposed in heating free condition. As a result, it is discovered that even in the case of low dose and high transmittance, reticle heating is hardly avoidable. It is also shown that there is a simple relationship among reticle heating, transmittance and exposure dose. Based on this relationship, the reticle heating is thought to be predicted if the transmittance and dose are fixed.
Intra-field CD uniformity control is one of hurdles in EUV lithography. Reflection imaging system intrinsic to EUV
causes CD non-uniformity especially in exposure field edge. To analyze dominant contributors to make this intra-field
CD non-uniformity in EUV lithography, influence of flare from adjacent fields and in-band and out of band refection
from reticle masking blind(REMA) and mask black border were investigated through intensive sampling of CD
measurement. Also mask border condition and REMA open settings are split into various settings to find out the impacts
from each contributor. Two ASML EUV scanners, alpha demo tool(ADT) and pre-production tool(PPT) are used for the
experiment. Fortunately, DUV out of band(OoB), reflection of REMA and the flare from adjacent fields are found to be
not significant in NXE3100. The results presented here lead us to the conclusion that the EUV refection from mask black
border is the main contributor and CD non-uniformity of the field edge can be overcome through optimized REMA
setting.
Extreme Ultra-Violet (EUV) lithography is almost only solution reachable for next-generation lithography below 30nm
half pitch with relative cost competitiveness. In this study, we investigate the feasibility of EUV lithography for applying
2X nm dynamic random access memory (DRAM) patterning. Very short wavelength of 13.5nm adds much more
complexity to the lithography process. To understand for challenges of EUV lithography for high volume manufacturing
(HVM), we study some EUV specific issues by using EUV full-field scanners, alpha demo tool (ADT) at IMEC and pre-production
tool (PPT) at ASML. Good pattern fidelity of 2X nm node DRAM has been achieved by EUV ADT, such as
dense line and dense contact-hole. In this paper, we report on EUV PPT performance such as resolution limit, MEEF,
across slit CD uniformity (CDU) and focus & exposure latitude margin with 2X nm node DRAM layers in comparison
with ADT performance. Due to less flare and aberration of PPT, we have expected that PPT shows good performance.
EUV lithography is the leading candidate for sub-32nm half-pitch device manufacturing. EUV Pre-Production Tool
(PPT) is expected to be available at the end of 2010. As EUVL era comes closer, EUVL infrastructure has to get mature
including EUVL mask stack. To reduce HV CD bias which comes from shadowing effect, thin mask stack has been
considered. We presented that EUVL mask with 58nm absorber height shows same printing performance with
conventional EUVL mask with 80nm absorber height in our previous work. CD change and pattern damage at the
exposure field edges due to light leakage from the neighboring fields were also demonstrated.
In this paper, optimal mask stack which shows lower H-V CD bias than conventional structure using 70-nm-thick
absorber is proposed. To find minimized absorber height for sub-32nm pattering experimentally, printing result of
conventional mask and thin mask stack with 1:1 L/S patterns will be compared. Further-on, we demonstrate the printing
result of the reticle which is designed to minimize CD error at the exposure field edges due to mask black border
reflectivity by reducing reflectivity from the absorber.
All the wafers are exposed at ASML Alpha Demo Tool (ADT) and Pre-Production Tool (PPT) S-litho EUV is used for
simulation.
Conventional EVUL mask has 80nm absorber height which brings considerable shadowing effect. H-V CD bias of 40nm
line and space by shadowing effect is more than 4nm, and that is expected to increase much more for narrower patterns
by simulation. However various reports have been presented on mask shadowing bias correction, experimental results
are not reliable to derive required mask bias correctly. Even more difficulty will arise when complex 2D structures are
taken into account. Therefore minimization of shadowing effect by reducing absorber thickness is desirable. To transfer
EUV lithography from experimental stage to HVM era, we need to find optimum absorber height of EUVL mask which
allows us less shadowing effect with minimum loss of process window.
In this paper, we present optimal absorber height of EUV mask which has been found in terms of shadowing effect and
process window by simulation and exposure. To find minimized absorber height experimentally, we will compare the
printing result of conventional and thin mask stack using simple 1:1 line and space and island patterns. Simulated H-V
CD bias and process window will be presented.
In the field of lithography technology, EUV lithography can be a leading candidate for sub-30 nm technology node.
EUVL expose system has different characteristics compared to DUV exposure system. EUV source wavelength is short
and no material is transparent to the source. So off-axis reflective optic system is used for patterning in place of on-axis
refractive system of DUV system. And different reticle design is needed that consists of 40 pair of Mo/Si multi layer
and absorber layer in place of conventional mask. Because of the oblique incidence on the mask, shadowing effect is
occurred such as pattern asymmetry, shift and pattern bias depending on pattern orientation. For non-telecentric
characteristics of EUV scanner, shadowing effect produces CD variation versus field position[1][2]. Besides, it is well
known that EUV scanner has bigger flare than conventional DUV scanner. Therefore, the correction of mask shadowing
effect and flare level are one of the important issues for EUV lithography.
In this paper, process window and MEF of EUV lithography has been examined by 3D mask simulation. CD
variation by shadowing is simulated for various pattern orientations. A shadowing correction method has been
calculated due to field position to reduce shadowing effect. And the correction effect is examined by simulation and
Experimental results. Principle of radial overlay shift due to field position is verified then the shift length of line and
space pattern is calculated.
Small contact holes are the most difficult structures for microlithography to print because it is sensitively affected by the process condition, pattern density and environment as well. Moreover, the patterning of very small contact hole features for the 60nm node DRAM device generation will be a difficult challenge for 248nm lithography. However, we have already demonstrated the applicability of thermal flow resist to print 80nm contact holes for DRAM device using 248nm lithography in previous studies. In this work, we study the potential for contact photoresist reflow to be used with 248nm photoresist to increase process windows of small contact dimensions at the 60nm node DRAM device generation (0.21 k1). With KrF 0.80NA scanner, resist flow process and layout optimization were carried out to achieve the contact hole patterning. And also the exposure condition was optimized. For a contact hole with CDs of 69nm +/- 10%, Focus-Exposure windows over the wafer are 0.25μm and 8%, respectively. In conclusion, we have successfully achieved the contact hole patterning with KrF resist flow process for the 60nm node DRAM device.
One of the crucial tasks of semiconductor process is reduction of manufacturing cost by shrinking the design rule with the help of fine patterning technologies. For high density DRAM application, we explored 0.29 k1 lithography with KrF 0.80NA scanner. Well-known lithography technologies such as asymmetric crosspole, dipole illumination and 6% attenuated PSMs were used for this experiment. Illumination source and mask layout optimization were carried out iteratively to meet CD target, and high contrast thin resist was applied to improve pattern fidelity. Some of the biggest challenges were coping with large MEEF and reducing simulation error. Abnormal non-open fail, probably due to large MEEF, was observed at a dense contact hole pattern. To cope with non-open fail, we tested multi-PSM which composed of alternating PSM along the x-axis direction and 6% attenuated PSM along the y-axis direction. Also we pushed sigma offset of illumination pupil more strongly than exposure tool's specification and there was no serious drawbacks of partial coherency extension. Accurate partial coherence measurement was important for obtaining target CDs and reducing OPC error. For some layers, unexpected simulation error was occurred especially at the patterns of peripheral circuit, therefore we had to calibrate simulation parameters of in-house tool and commercial tool (Solid-C) for OPC simulation. Finally we successfully demonstrated 0.29k1 KrF lithography by showing process yield over 58% in 512Mb DRAM having design rule of 90nm. Based on the results we obtained, we can conclude that 0.29k1 lithography is quite feasible for mass production and 60nm design rule DRAM devices can be manufactured with ArF dry 0.93NA. Since dry 0.93NA corresponds to 1.33NA in ArF water immersion with respect to k1, we can expect that it is possible to fabricate 42nm DRAM devices with ArF immersion lithography.
248nm wave lithography process is being pushed and extended to sub 130nm node by continuous RET(Resolution Enhancement Technique) improvement. By applying various kind of RET such as exposure lens NA(Numerical Aperture) enlargement, more strong OAI(Off Axis Illumination), elaborated OPC(Optical Proximity Correction), and high performance resist, we still can’t give up for 248nm wave technology 130nm node and beyond. But there are some major challenges to reduce MEEF(Mask Error Effect Factor) and understand lens aberrations. This paper will try to find out mutual relationship between 248nm 0.8NA exposure lens aberration and actual patterns. Influence of lens aberration on patterning characteristic will be investigated by using in house simulation tool.
95nm KrF lithography has been developed for 512 Mb DRAM. KrF 0.80NA scanner was used to print 190nm pitch patterns and this means the process factor k1 is 0.306. Crosspole illumination was used to print critical layers, which has four poles on x and y-axis. To improve CD uniformity of critical layers we also used fogging effect corrected (FEC) reticles and thin photo resist process, which needs the hard mask etching process to overcome poor dry etch resistance. For 95nm DRAM cell patterns, we could get more than 8% exposure latitude (EL) and 0.3 μm depth of focus (DOF). With FEC masks and optimized resist process, CD uniformity of word line layer printed on wafer was less than 10nm. Overlay accuracy of critical layers is mostly less than 25nm. However at core and periphery area of DRAM the extreme off-axis illumination like crosspole brought poor process latitude in weak zone duties and therefore the hard optical proximity correction (OPC) work was required. In a real integration other novel technologies are used such as gap-filling for STI and ILD processes, Wsi gate, W bit line and SAC processes. This paper reported only lithographic performance for printing 95nm DRAM patterns. Consequently KrF lithography is still promising technology to print sub 100nm node DRAM.
Most chip makers want KrF lithography is extended below sub 100nm lithography due to cost and process stability, even though ArF lithography has been growing and its performance is enough to apply to 100nm node. But process control of KrF lithography will become difficult at sub 100nm node era because of difficulty of mask making, accuracy of optical proximity correction (OPC), lens effects caused by strong off-axis illumination, need more tool accuracies than ever, and so on.
We have evaluated 0.33k1 ArF lithography using 0.63NA scanner to develop 100 nm DRAM. ArF resist problems were resist pattern shrinkage during CD SEM measurement, resist pattern collapse during wet development and poor etch resistance. Off-Site Measurement (OSM) method has been developed for decreasing pattern shrinkage. With OSM method, 8nm of CD shrinkage was down to 2nm for 100nm L/S patterns. We have found a proper BARC material that prevents resist patterns falling down. Lack of etch resistance was compensated by hard mask. With W/SiN hard mask, acrylate- type resist patterns were transferred well into W/poly-Si gate patterns. We have simulated process window of critical DRAM cell patterns (isolation, gate, bit line contact, storage node) in the simple off-axis illumination (OAI) and optical proximity correction (OPC) conditions based on single exposure. Simulation results were verified by lithography tests and it turned out that 0.33k1 process was possible with exposure latitude of above 10% and focus latitude of more than 0.4 micrometers . 0.33k1 ArF lithography was successfully implemented into 100 nm DRAM with CD uniformity of 10nm (3 (sigma) ) and overlay accuracy of 30 nm (mean +3 (sigma) ). We have also evaluated double exposure technique using dipole illumination targeting 90 nm in order to see the possibility of 0.29k1 process. 0.29k1 process was also likely to be possible, although some specific improvements were recommended for the wider process window. From the simulation and resist patterning results, we believe that 0.85 NA lens will be able to extend ArF lithography into 75 nm by single exposure technology using crosspole illumination (0.33k1 process) and 65 nm by double exposure technology using dipole and crosspole illumination (0.29k1 process).
To achieve 100 nm DRAM full chip with 0.63 NA ArF lithography we used a new type of off-axis illumination, crosspole illumination which has four poles on axis. For lower than 0.33 k1 process double exposure technology has been introduced which is exposing cell and core/periphery region separately with different illumination conditions. But with crosspole 0.33 to 0.31 k1 process could be possible without double exposure. Advantages and disadvantages of crosspole illumination and successful result of printing 100 nm DRAM full chip are shown in this paper. And also ArF lithography issues occurred during processing DRAM full chip are reported such as lens heating, contamination optics and reticles, overlay errors induced by electron beam curing process and so on. To simulate patterning result we used HOST (Hynix OPC simulation tool) based on diffused aerial image model (DAIM). For all kinds of 100 nm DRAM patterns, we could get sufficient process latitude, more than 10% exposure latitude (EL) and 0.4 micrometers depth of focus (DOF). Also 95 nm DRAM cell patterns could be printed successfully with crosspole single exposure and this shows with 0.75 NA and 0.85NA ArF tools we can print 80 nm and 70 nm DRAM patterns, respectively.
The feasibility of sub-100 nm patterning with ArF lithography has been studied. We used ArF 0.63 NA exposure tool and investigated process windows. In-house resist (DHA-H110) and bottom anti-reflective coating material (HEART004) are used as well as commercial ones. To print sub-100 nm patterns we used the resolution enhancement technology (RET) that is extreme off-axis illumination (OAI) such as dipole and strong annular. To predict the result and compare with experimental data our simulation tool HOST (Hyundai OPC Simulation Tool) based on diffused aerial image model (DAIM) was used. Although the infrastructure of ArF lithography is not mature enough, we got a good result. For 95 nm and 90 nm patterns we could get more than 8% exposure latitude (EL) and 0.3 micrometer depth of focus (DOF). For isolated gate pattern sub-70 nm pattern was printed and we have got the characteristics of 70 nm periphery transistor. For contact hole (C/H) patterns it was more effective to use KrF lithography because resist thermal flow process (RFP) can be used to shrink C/H size. With RFP we printed up to 50 nm C/H patterns. Through this study we found that k1 value can be reduced up to 0.29 and ArF lithography can be applied for 70 nm node with high contrast resist and high NA exposure tool.
In this paper we investigated the feasibility of printing sub-0.13 micrometers device patterns with ArF and KrF lithography by using experiment and simulation. To do this we evaluated various cell structures with different sizes from 0.26 micrometers to 0.20 micrometers pitch. In experiment 0.60NA ArF and 0.70NA KrF exposure tools, commercial and in house resists and bottom anti-reflective coating (BARC) materials are used. To predict and compare with experimental data we also used our developed simulation tool HOST base don diffused aerial iamge model. We found that ArF lithography performance is a little bit better than KrF and therefore 0.70NA KrF lithography can be used up to 0.12 micrometers design rule device and 0.60NA ArF lithography can be used up to 0.11 micrometers . But to get more than 10 percent expose latitude, 0.13 micrometers with KrF and 0.12 micrometers with ArF are the minimum design rule size. However to obtain process margin we had to use extreme off-axis illumination (OAI) which results in large isolated- dense bias and poor linearity including isolated pattern. Using higher NA can reduce ID bias and mask error factor. For contact hole it is more effective to use KrF lithography because resist thermal flow process can be used to shrink C/H size. Our developed ArF resist and BARC shows good performance and we can reduce k1 value up to 0.34. Through this study we verified again that ArF lithography can be applied for sub-0.13 micrometers device through sub-0.10 micrometers with high contrast resist and 0.75NA exposure tool.
We estimated the process margins of various cell structures and process problems for full chip process under extreme resolution limit of exposure tool. Therefore, optimizing off axis illumination (OAI) condition for various structures obtained the fine pattern and wider process margin using simulation and experiment. From our experiment, we should use as higher numerical aperture (NA), smaller R and smaller as possible to reduce critical dimension (CD) difference between dense and isolated patterns. Process margins are obtained more than 8 percent exposure latitude (EL) and 0.5 micrometers depth of focus (DOF) for each cell. However, we can consider using of attenuated phase shift mask to improve the exposure and DOF margin. We find that real full chip process induces the critical problems such as isolated line (I/L) and space (I/S) pattern variation due to lens aberration, partial coherence effect, mask error effect, and optical proximity effect. These effects play a role to determine the design rule of cell and periphery structures. In spite of good lens quality, variation of I/L and I/S pattern for various exposure conditions is almost 40nm or more compared to line and space pattern. These phenomena are becoming the critical issue to fulfill the full chip process of 130nm lithography. By optimizing mask error effect, isolated and dense pattern bias, and OAI, we can achieve 130nm technology with 248nm KrF lithography.
With KrF and off-axis illumination (OAI) technique we should set up 150nm lithography process without using phase shift mask. But isolated-dense bias (ID bias) makes 150nm lithography process difficult. We investigated ID bias trend at different OAI condition and found that it could be reduced by optimizing OAI condition. We represent OAI as quadrupole center (sigma) R and pole size radius r. With high NA, small R and small r we can reduce ID bias but cannot eliminate completely at 150nm lithography. Also we found out that ID bias of duty patterns are more severe than that of dense and isolated patterns. Using OAI at a certain space width between lines, the width of lien has its minimum. This line thinning phenomena at this weak zone depends on OAI condition such as NA, R and coherence value. We compared simulation data with experimental result and could see the same phenomena at simulation data. Therefore OPC is necessary to avoid this weak zone. By experiment and simulation with NA higher than 0.65 and Optical Proximity Correction, we could set up 150nm lithography process with below 0.20micrometers periphery pattern design rule.
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