Lithography faces today many challenges to meet the ITRS road-map. 193nm is still today the only existing
industrial option to address high volume production for the 22nm node. Nevertheless to achieve such a resolution, double
exposure is mandatory for critical level patterning. EUV lithography is still challenged by the availability of high power
source and mask defectivity and suffers from a high cost of ownership perspective. Its introduction is now not foreseen
before 2015.
Parallel to these mask-based technologies, maskless lithography regularly makes significant progress in terms of
potential and maturity. The massively parallel e-beam solution appears as a real candidate for high volume
manufacturing. Several industrial projects are under development, one in the US, with the KLA REBL project and two in
Europe driven by IMS Nanofabrication (Austria) and MAPPER (The Netherlands).
Among the developments to be performed to secure the takeoff of the multi-beam technology, the availability of a
rapid and robust data treatment solution will be one of the major challenges. Within this data preparation flow, advanced
proximity effect corrections must be implemented to address the 16nm node and below. This paper will detail this
process and compare correction strategies in terms of robustness and accuracy. It will be based on results obtained using
a MAPPER tool within the IMAGINE program driven by CEA-LETI, in Grenoble, France. All proximity effects
corrections and the dithering step were performed using the software platform Inscale® from Aselta Nanographics. One
important advantage of Inscale® is the ability to combine both model based dose and geometry adjustment to accurately
pattern critical features. The paper will focus on the advantage of combining those two corrections at the 16nm node
instead of using only geometry corrections. Thanks to the simulation capability of Inscale®, pattern fidelity and
correction robustness will be evaluated and compared between the correction strategies. This work will be lead on the
most critical layers of the 16nm integrate circuits layouts which are contact and metal 1. Finally the aim of this paper is
to demonstrate that a complete data preparation flow including advanced proximity effects corrections, simulation and
verification capabilities is available for the maskless lithography at the 16nm node and below, through the direct write
version of Inscale®. This data preparation platform is already in use in several laboratories for direct write processes.
A new correction approach was developed to improve the process window of electron beam lithography and push its
resolution at least one generation further using the same exposure tool. An efficient combination of dose and geometry
modulation is implemented in the commercial data preparation software, called Inscale®, from Aselta Nanographics.
Furthermore, the electron Resolution Improvement Feature (eRIF) is tested, which is based on the dose modulation and
multiple-pass exposure, for not only overcoming the narrow resist process windows and disability of exposure tool but
also more accurate correction of exposure data in the application of sub-35nm regime. Firstly, we are demonstrating the
newly developed correction method through the comparison of its test exposure and the one with conventional dose
modulation method. Secondly, the electron Resolution Improvement Feature is presented with the test application for
complementary exposure and with the application of real design, specifically for sub-30nm nodes. Finally, we discuss
the requirements of data preparation for the practical applications in e-beam lithography, especially for future technology
nodes.
Electron Beam Direct Write (EBDW) lithography is used in the IC manufacturing industry to sustain optical
lithography for prototyping applications and low volume manufacturing. It is also used in R&D to develop advanced
technologies, ahead of mass production. As microelectronics is now moving towards the 32nm node and beyond, the
specifications in terms of dimension control and roughness becomes tighter. In addition, the shrink of the size and pitch
of features significantly reduces the process window of lithographic tools. In EBDW, the standard proximity effects
corrections only based on dose modulation show difficulties to provide the required Energy Latitude for patterning
structures designed below 45nm. A new approach is thus needed to improve the process window of EBDW lithography
and push its resolution capabilities.
In previous papers, a new writing strategy based on multiple pass exposure has been introduced and optimized to
pattern critical dense lines. This new technique consists in adding small electron Resolution Improvement Features
(eRIFs) on top of the nominal structures. Then this new design is exposed in two successive passes with optimized doses.
Previous studies were led to evaluate this new writing technique and establish rules to optimize the design of the eRIF.
Significant improvements have already been demonstrated on SRAM and Logic structures down to the 16nm node.
These results were obtained with a tool dedicated to the 45nm node. The next step of this work is thus to automatically
implement the eRIF to correct large-scale layouts.
In this paper, a new data preparation flow is set up for EBDW lithography. It uses the eRIF solution as a full
advanced correction method for critical structures. The specific correction rules established in our previous studies are
implemented to improve the CD control and the patterning of corners and line ends. Moreover, the dose and shape of the
eRIFs are automatically tuned to best fit the nominal design. This work is done with "INSCALE®", the new data
preparation software from ASELTA Nanographics. This data preparation flow is then applied on layouts down to the
22nm node. Comparisons with the standard dose modulation flow demonstrate that adding eRIFs significantly improves
the process window and thus the resolution of e-beam tools. It also shows that the multiple pass exposure technique can
be used as a specific correction method on large scale layouts.
KEYWORDS: Electroluminescence, Modulation, Line edge roughness, Electron beam lithography, Semiconducting wafers, Logic, Metals, Etching, Electron beam direct write lithography, Electron beams
Electron Beam Direct Write lithography is used in the IC manufacturing industry to sustain optical lithography for
prototyping applications and low volume manufacturing. It is also used in R&D to develop the technological nodes
ahead of mass production. As microelectronics is now moving towards the 32nm node and beyond, the need to
accurately control the dimensions and the roughness of the features becomes tighter. As a consequence the requirements
in terms of process window and resolution for the electron beam tools are more stringent. However the standard
proximity effects corrections show difficulties to provide the required energy latitude for the sub-22nm nodes. A new
approach is thus required to improve the patterning capabilities of electron beam lithography. In previous papers a new
writing strategy based on multiple pass exposure has been introduced and optimized to pattern critical dense lines. This
technique consists in adding small electron Resolution Improvement Features (eRIF) on top of the nominal structures.
Previous studies have demonstrated that the energy latitude and the writing time can be optimized by tuning the design
of the eRIF. A methodology to implement the eRIF on dense lines has also been established. The goal of this paper is to
extend the use of the multiple pass exposure strategy to more complex designs taken from products layouts. The most
critical layers of SRAM and Logic layouts down to the 16nm node are corrected with this advanced correction technique.
The results from wafer exposures show that the edge roughness of the features is decreased and the energy latitude of our
process is multiplied by two for each SRAM layer. Thanks to these improvements of the patterning capabilities of our
electron beam tool, a gain in resolution of one technological node is achieved. Finally a method is proposed to implement the multiple pass exposure within an automated data preparation flow.
KEYWORDS: Electroluminescence, Electron beam direct write lithography, Standards development, Electron beam lithography, Optical lithography, Semiconducting wafers, Electron beams, Lithography, Line edge roughness, Optics manufacturing
Electron beam direct write lithography is used in the ASIC manufacturing industry to sustain optical lithography for
prototyping applications, low volume production and for the development of the next technological nodes. However the
standard proximity effects corrections based on dose modulation are not sufficient to provide the patterning accuracy
required for the sub-32nm nodes. New methods are needed to push the resolution capabilities of electron beam
lithography. In a previous paper, a new writing strategy based on multiple pass exposure has been introduced. It consists
in adding small electron Resolution Improvement Features (eRIF) atop the nominal features. Thanks to this new method,
critical lines have been patterned with enlarged energy latitude. In this paper, multiple pass exposure is applied to the
sub-32nm nodes. The influence of the design of the eRIF is analysed in detail. The best conditions in terms of dose, size
and placement of the eRIF are used to establish a methodology to optimize this new strategy. Using multiple pass
exposure, the energy latitude was increased up to about 20% which is three times the energy latitude of the standard
exposure. Then the impact of multiple pass exposure on the writing time of the electron beam tool is studied. It appears
that a compromise has to be found between the writing time and the improvement of the energy latitude. Finally it is
shown that the resolution capabilities of the electron beam lithography can be increased using the multiple pass exposure
strategy.
KEYWORDS: Data modeling, 3D modeling, Electron beam direct write lithography, Point spread functions, Critical dimension metrology, Model-based design, Geometrical optics, Cadmium, Error analysis, Virtual reality
We demonstrate a flow for e-beam proximity correction (EBPC) to e-beam direct write (EBDW) wafer manufacturing
processes, demonstrating a solution that covers all steps from the generation of a test pattern for (experimental or virtual)
measurement data creation, over e-beam model fitting, proximity effect correction (PEC), and verification of the results.
We base our approach on a predictive, physical e-beam simulation tool, with the possibility to complement this with
experimental data, and the goal of preparing the EBPC methods for the advent of high-volume EBDW tools.
As an example, we apply and compare dose correction and geometric correction for low and high electron energies on
1D and 2D test patterns. In particular, we show some results of model-based geometric correction as it is typical for the
optical case, but enhanced for the particularities of e-beam technology.
The results are used to discuss PEC strategies, with respect to short and long range effects.
KEYWORDS: Electroluminescence, Line edge roughness, Electron beam lithography, Electron beam direct write lithography, Modulation, Scattering, Optical lithography, Point spread functions, Standards development, Lithography
Electron beam direct write lithography is known for its high resolution capabilities, which enables studies ahead of the technology in production. That is why this technique is used for many years in laboratories for R&D. Recently it was shown that electron beam lithography can be integrated within the flows of the microelectronics industry for prototyping applications, low volume production and to support optical lithography for ASIC manufacturing. Moreover recent lithography workshops highlighted that the multi beam solution is identified as one potential technique for next generation lithography techniques to meet the requirements of sub-32nm technological nodes. The present proximity correction methods for electron beam lithography are based on the standard dose modulation principle. However these methods cannot properly ensure a sufficient control of the patterning of the most critical designs.
To push the resolution capability of electron beam lithography, a new correction method is proposed. It consists in a multiple pass exposure strategy. For example instead of patterning a line in one pass (standard exposure), the pattern is split in several basic blocks with potential overlaps exposed in several passes and with an adapted dose. Compared to standard exposure, this solution provides an improved process window and a better control of the critical dimensions. We could achieve energy latitude of 22.2% and we improved the line edge roughness by 27% on 45nm dense lines (line width equal to space) with this method.
KEYWORDS: Vestigial sideband modulation, Electron beam direct write lithography, Electron beam lithography, Beam shaping, Scanning electron microscopy, Standards development, Lithography, Prototyping, Semiconducting wafers, Electron beams
The ever more demanding requirements in the semiconductor manufacturing sector together with the increasing mask making costs and cycle times call for new lithographic solutions. Electron beam lithography has shown its superior performance and flexibility in advanced patterning applications. It enables already today process and technology developments ahead of the ITRS roadmap, which addresses currently the 32nm and 22nm node or even below. Thus electron beam direct write (EBDW) can avoid the high costs and delay times related to the advanced masks required for critical layers.
On the other side EBDW faces the concerns regarding its throughput, which bases upon the inherited sequential exposure method. A solution to improve the throughput performance offers the implementation of the cell projection method as already materialized in the Vistec SB3055 tool. In addition to the variable shape beam technology, which can project regular structures (rectangles, slants and triangles) only, cell projection is able to image complex structures. Thus, structures that would have required a multiple of regular shots are now projected in one single shot. Thanks to this approach not only the shot count is noticeably reduced, but also the overall throughput is increased. First experimental and simulation results show an improvement of a factor of about 3X. Nevertheless, the final throughput gain strongly depends on the pattern and data structure itself.
Combining high resolution variable shape beam technology with the cell projection feature allows advanced R&D and small volume and prototyping applications to be performed with one system. The Vistec SB3055 features the high resolution capability of variable shape beam lithography and incorporates the advantages of the cell projection technology. Owing to this new option we are able to improve the throughput for standard design features while maintaining the required high accuracy of our exposure system. Beside this, the combination of cell projection and standard shape beam technology still offers a high degree of flexibility as the key advantage of EBDW.
On the Vistec SB3055 system we have performed different resolution tests serving as comparison between cell projection and standard shape beam. In this paper we will present the resolution capability obtained with cell projection on test structures as well as the general accuracy achieved for real patterns.
Due to the ever-increasing cost of equipment and mask complexity, the use of optical
lithography for integrated circuit manufacturing is increasingly more complex and expensive.
Recent workshops and conferences in semiconductor lithography underlined that one alternative
to support sub-32nm technologies is mask-less lithography option using electron beam
technology. However, this direct write approach based on variable shaped beam principle (VSB)
is not sufficient in terms of throughput, i.e. of productivity. New direct write techniques like
multibeam systems are under development, but these solutions will not be mature before 2012.
The use of character/cell projection (CP) on industrial VSB tools is the first step to deal with the
throughput concerns. This paper presents the status of the CP technology and evaluates its
possible use for the 45nm and 32nm logic nodes. It will present standard cell and SRAM
structures that are printed as single characters using the CP technique. All experiments are done
using the Advantest tool (F3000) which can project up to 100 different cells per layer. Cell
extractions and design have been performed with the design and software solution developed by
D2S. In this paper, we first evaluate the performance gain that can be obtained with the CP
approach compared to the standard VSB approach. This paper also details the patterning
capability obtained by using the CP concept. An evaluation of the CD uniformity and process
stability is also presented. Finally this paper discusses about the improvements of this technique
to address high resolution and to improve the throughput concerns.
KEYWORDS: Optical alignment, Semiconducting wafers, Optical lithography, Electron beams, Electron beam direct write lithography, Lithography, Signal to noise ratio, Overlay metrology, Signal detection, Wafer testing
With shrinking dimensions in the semiconductor industry the lithographic demands are exceeding the parameters of the
standard optical lithography. Electron beam direct write (EBDW) presents a good solution to overcome these limits and
to successfully use this technology in R&D as well as in prototyping and some niche applications. For the industrial
application of EBDW an alignment strategy adapted to the industrial standards is required to be compatible with optical
lithography. In this context the crucial factor is the overlay performance, i.e. the maturity of the alignment strategy under
different process conditions. New alignment marks improve the alignment repeatability and increase the window of the
signal-to-noise ratio towards smaller or noisier signals. Particularly the latter has proved to be a major contribution to a
higher maturity of the alignment. A comparison between the double cross and the new Barker mark type is presented in
this paper. Furthermore, the mark reading repeatability and the final overlay results achieved are discussed.
With the willingness of the semiconductor industry to push manufacturing costs down, the mask
less lithography solution represents a promising option to deal with the cost and complexity concerns
about the optical lithography solution. Though a real interest, the development of multi beam tools still
remains in laboratory environment. In the frame of the seventh European Framework Program (FP7), a
new project, MAGIC, started January 1st 2008 with the objective to strengthen the development of the
mask less technology. The aim of the program is to develop multi beam systems from MAPPER and
IMS nanofabrication technologies and the associated infrastructure for the future tool usage. This paper
draws the present status of multi beam lithography and details the content and the objectives of the
MAGIC project.
The beam energy is a driving design parameter for electron beam lithography systems. To be able to compare the
differences of low kV (5 kV) and high kV (100 kV) for a high-throughput system the limitations of both types of systems
are evaluated. First the effect on the CD uniformity and throughput is analyzed. For any shot noise limited system the
dose that is needed to obtain a required CD uniformity can be calculated. This dose depends on the total spot size and the
efficiency of the electrons in the resist. For a smaller spot less dose is required than for a large spot. The current in a
single beam is also determined by the spot size. A larger spot has more current. With these parameters an optimization of
the required dose, spot size and single beam current can be made. It is found that although for high kV it is easier to
create a small spot with a high current the low resist-exposure efficiency of the high-energy electrons limits the
throughput, because the required dose is large. It is also found that for 10 wafers per hour multiple lenses or columns are
required. For practical reasons (a high kV lens cannot be made as small as a low kV lens) there is a clear preference for
the use of low energy in high-throughput systems. Another aspect that is crucial in the lithography process is the overlay.
One of the main differences between high and low energy systems is the power that is dissipated in the wafer and the
resulting error due to expansion. It is found that for both energies wafer heating is an issue, but for low kV there seem to
be solutions, while for high kV the problem is 30 times bigger.
KEYWORDS: Modulation, Critical dimension metrology, Electron beam direct write lithography, Point spread functions, Electron beam lithography, Cadmium sulfide, Electron beams, Optical lithography, Manufacturing, Backscatter
After the successful results obtained in the last few years, electron beam direct write (EBDW) lithography for use in integrated circuit manufacturing has now been demonstrated. However, throughput and resolution capabilities need to be improved to push its interest for fast cycle production and advanced research and development applications. In this way, the process development needs good patterns dimensional accuracy, i.e., a better control of the proximity effects caused by backscattering electrons and others phenomenon. In this work, the limitations of the dose modulation method are investigated through the change of dose number steps and the use of a more accurate point spread function. To continue reducing feature sizes, a method to provide a complementary correction to the dose modulation solution is proposed. This rule-based electron beam proximity correction, or REBPC, provides good results down to 40 nm.
KEYWORDS: Monte Carlo methods, Point spread functions, Electron beam direct write lithography, Optical simulations, Electron beam lithography, Electron beams, Convolution, Scattering, Photoresist processing, Laser scattering
Electron Beam Direct Write (EBDW) is involved today in advanced devices
manufacturing and technology node development. As a consequence, EBDW is supporting an
increasing number of technologies and several layers per technology. In this context, an
EBDW simulator can strongly help this development study and reduce process development
cycle time. Today, available EBDW simulators are based on the use of a Point Spread
Function (PSF) to describe the energy absorbed into the resist during exposure and resist
models. Beside a constant improvement of these models limitations are observed in simulation
of sub-45nm nodes. In this paper, several simulation methods are investigated with the
purpose to build a simulation method relevant for sub-45nm nodes. The limitations of classical
EBDW simulation based on a full process flow simulation are evaluated for line width below
100nm. Then, a reduced process flow simulation limited to the exposure step is investigated
with the use of both a simulated PSF and an empirical PSF. We will see that the approach to
use an empirical PSF with the reduced process flow simulation has good predicting
capabilities in simulating structures down to 40nm.
For the 90nm node and below the Depth of Focus (DOF) becomes more and more critical. To increase the DOF lithographers have introduced resolution enhancement techniques (RET) such as sub-resolution assist features (SRAF) which are today largely used by the semiconductor industry for 120nm, 90nm and 65nm technologies. Bruce Smith [1] showed that the improvement of the DOF from the adding of the scatter bars depends on the position of the iso-focal intensity threshold compared to the critical dimension (CD) intensity threshold. When these two points are at the same position the DOF is maximum. This paper shows the theoretical link between the iso-focal point and the evolution of the DOF. It will be shown that the link between these two parameters can be described by a simple equation. The theoretical expression shows a good estimation of the DOF evolution. The theoretical evolution of the iso-focal point is obtained from the expressions of the intensity. We will see that its variation is basically a function of the transmission and of the diffraction orders interfering. The expressions giving the evolution of the iso- focal point follows the trends obtained by conventional lithography simulation. We have studied the theoretical evolution of the iso-focal point for the mask types used by the semiconductor industry such as binary, alternating and attenuated phase shift masks. We will also see how this evolution of the iso-focal point impacts the depth of focus and that the DOF can be improved by an adjustment of the iso-focal point.
With the strong increase of mask complexity and associated price for each new technology node, mask less lithography represents more and more an interesting and complementary alternative for ASIC manufacturing especially in the fields of low volume and leading eadge technology applications. In the semiconductor business where prices and cycle time are constantly pressured, the capability and flexibility of the electron beam direct write offer an effective real cost and cycle time opportunity thanks to its high-resolution capability but also to its ability to print, modify or correct design everywhere in a circuit. This paper highlights application examples where the advantages of this lithography solution are demonstrated for advanced research and development application with the patterning of 45 nm SRAM and for the fast validation of architecture designs. This work confirms that mask less lithography can be transparently placed into production environment, in association with the "golden" optical lithography reference.
KEYWORDS: Line width roughness, Electron beam direct write lithography, Semiconducting wafers, Electron beam lithography, Electron beams, Manufacturing, Etching, Photoresist processing, Coating, Semiconductors
Electron Beam Direct Write (EBDW) lithography represents a low cost and a rapid way to start basic studies for advance devices and process developments. Patterning for sub-45nm node technology requires the development of high performance processes. Different alternatives for the improvement of EBDW lithography are investigated in this paper for the ASIC manufacturing on 300mm wafer size. Among them, process development has been tuned for clear field equivalent level to improve both line width roughness by monitoring post applied bake conditions, and both process window by specific design correction. Concerning dark field level, process resolution has been improved by a shrinkage technique.
Laurent Pain, M. Jurdit, Yves LaPlanche, J. Todeschini, Serdar Manakli, G. Bervin, Ramiro Palla, A. Beverina, R. Faure, X. Bossy, H. Leininger, S. Tourniol, M. Broekaart, F. Judong, K. Brosselin, P. Gouraud, Veronique De Jonghe, Daniel Henry, M. Woo, Peter Stolk, B. Tavel, F. Arnaud
The introduction of Electron Beam Direct Write lithography into production represents a
challenging alternative to reduce cost and cycle time increase induced by the introduction of new
generation nodes. This paper details the development work performed to insert transparently direct
write lithography process and alignment strategies into CMOS process flows. Finally, this
interchangeability between E-Beam and optical lithography steps offers a complete flexibility for
device architecture validation and allowed the development of a complete low cost 65nm platform
including low-power and general-purpose applications.
To follow the accelerating ITRS roadmap, microprocessor and DRAM manufacturers are on their way to introduce the alternating phase shift mask (APSM) to be able to print the gate level on sub-130-nm devices. This is done at very high mask costs, long cycle times, and poor guarantees to get defect-free masks. Nakao et al. have proposed a new resolution enhancement technique (RET). They have shown that sub-0.1-µm features could be printed with good process latitudes using a double binary mask printing technique. This solution is very interesting, but is applicable to isolated structures only. To overcome this limitation, we have developed an extension of this technique called complementary double exposure (CODE). It combines Nakao's technique and the use of assist features that are removed during a second subsequent exposure. This new method enables us to print isolated as well as dense features on advanced devices using two binary masks. We describe all the steps required to develop the CODE application. The layout rules generation and the impact of the second mask on the process latitude have been studied. Experimental verification has been done using 193-nm 0.63 and 0.75 numerical aperture (NA) scanners. The improvement brought by quadrupole or annular illuminations combined with CODE has also been evaluated. Finally, the results of the CODE technique, applied to a portion of a real circuit using all the developed rules, are shown.
In a previous paper, we have proposed the CODE (Complementary Double Exposure) technique. A new manufacturable Reticle Enhancement Technique (RET) using two binary masks. We have demonstrated the printability of 80nm dense (300nm pitch), semi-dense and isolated lines using the CODE technique and showed good printing results using a 0.63NA ArF scanner. In a more recent article we described all the steps required to develop the CODE application: the binary decomposition and the solutions developed in order to compensate adequately for line end shortening. This study was done based on aerial image simulations only. In this paper, we will give experimental results for printing complex two-dimensional structures for the high performance version of a 90nm ground rule, 240nm minimal pitch process, using the CODE technique. The results of depth of focus (DOF), energy latitude (EL) and mask error enhancement factor (MEEF) through pitch, and end-cap correction will be discussed, for quadrupole and annular illumination using a 193nm 0.70NA exposure tool. The CODE technique, not only because of a lower cost but also because of its performance, could be a good alternative to the alternating PSM technique, having less design penalties and a better mask making cycle time.
xIn order to address some specific issues related to gate level printing of the 0.09μm logic process, the following mask and illumination solutions have been evaluated. Annular and Quasar illumination using binary mask with assist feature and the CODE (Complementary Double Exposure) technique. Two different linewidths have been targeted after lithography: 100nm and 80nm respectively for lowpower and high-speed applications. The different solutions have been compared for their printing performance through pitch for Energy Latitude, Depth of Focus and Mask Error Enhancement Factor. The assist bar printability and line-end control was also determined. For printing the 100nm target, all tested options can be used, with a preference for Quasar illumination for the gain in Depth of Focus and
MEEF. For the 80nm target however, only the CODE technique with Quasar give sufficient good results for the critical litho parameters.
In a recent paper, we proposed a new manufacturable Reticule Enhancement Technique (RET) using two binary masks, called CODE (Complementary Double Exposure). We demonstrated the printability of 80nm dense (300nm pitch), semi-dense and isolated lines using this technique and showed good performance using an ArF 0.63NA scanner. To be able to use the CODE RET in production, we must be able to handle complex two-dimensional structures as well. In this paper we study the representative two-dimensional complex structures of a circuit in order to have a complete overview of this technique. We analyze the impact of the asymmetrical apertures and the impact of the 2nd mask overlap to the 1st mask. We show that asymmetrical apertures impact the line width of the non-critical lines. We also show that the 2nd mask has not only the role of protecting the exposed part. It also contributes strongly to the printability of the complex structures by correcting the defects of the 1st exposure. Finally, we show the results of CODE technique applied to a portion of a real circuit using all the developed rules.
To follow the accelerating ITRS roadmap, microprocessor and DRAM manufacturers have introduced the Alternating Phase shift mask (Alt.PSM) resolution enhancement technique (RET) in order to be able to print the gate level on sub 130nm devices. This is done at very high mask costs, a long cycle time and poor guarantee to get defect free masks. S. Nakao has proposed a new RET. He showed that sub 0.1um features could be printed with good process latitudes using a double binary mask printing technique. This solution is very interesting, but is applicable to isolated structures only. To overcome this limitation, we have developed an extension to this technique called CODE. This combines Nakao's technique and the use of assist features removed in a second subsequent exposure. This new solution enables us to print isolated as well as dense features on advanced devices using two binary masks. This paper will describe all the steps required to develop the CODE application. (1) Determination of the optimal optical settings, (2) Determination of optimal assist feature size and placement, (3) Layout rules generation, (4)Application of the layout rules to a complex layout, using the Mentor Graphics Calibre environment, (5) Experimental verification using a 193nm 0.63NA scanner.
The insertion point for the first scattering bar is a key point in the development of a process using assist features, because this semi dense feature will determine the overall depth of focus of the process. A study of the parameters, which influence the choice of this insertion point, has been performed using a 0.63 NA 193 nm scanner for a 100 nm CD target after litho. The impact of the scattering bar on: Depth of Focus, Energy Latitude, Mask Error Enhancement Factor, printability, and the effect of scattering bar line width variation on main feature described by a parameter called AFMEEF will be discussed in this paper. The optimal insertion point for the first scattering bar will strongly depend on the litho-graphic process and the mask parameters. A model is proposed to determine the optimal insertion point, as function of the dose, focus budget, minimal allowed scatterbar width, and mask CD dispersion for both scattering bars and main features.
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