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In our previous work, such atomic order controllability was viable in complemented technique with etching and deposition [2]. Overlay issue form major potion in yield management, therefore, entire solution is needed keenly including alignment accuracy on scanner and detectability on overlay measurement instruments. As EPE (Edge placement error) was defined as the gap between design pattern and contouring of actual pattern edge, pattern registration in single process level must be considerable. The complementary patterning to fabricate 1D layout actually mitigates any process restrictions, however, multiple process step, symbolized as LELE with 193-i, is burden to yield management and affordability. Recent progress of EUV technology is remarkable, and it is major potential solution for such complicated technical issues. EUV has robust resolution limit and it must be definitely strong scaling driver for process simplification. On the other hand, its stochastic variation such like shot noise due to light source power must be resolved with any additional complemented technique.
In this work, we examined the nano-order CD and profile control on EUV resist pattern and would introduce excellent accomplishments.
In this paper, we will report that photoresist smoothing work in an efficient way to pattern fidelity control in self-aligned type multiple patterning.
For the “cut” pattern, Design-Source-Mask Optimization (DSMO) has been demonstrated to be effective at the 20nm node and below.[2,3,4] Single patterning was found to be suitable down to 16nm, while double patterning extended optical lithography for cuts to the 10-12nm nodes. Design optimization avoided the need for triple patterning. Lines can be patterned with 193nm immersion with no complex OPC. The final line dimensions can be achieved by applying pitch division by two or four.[5]
In this study, we extend the scaling using simplified OPC to the 7nm node for critical FEOL and BEOL layers. The test block is a reasonably complex logic function with ~100k gates of combinatorial logic and flip-flops, scaled from previous experiments.
Simulation results show that for cuts at 7nm logic dimensions, the gate layer can be done with single patterning whose minimum pitch is 53nm, possibly some of the 1x metal layers can be done with double patterning whose minimum pitch is 53nm, and the contact layer will require triple patterning whose minimum pitch is 68nm. These pitches are less than the resolution limit of ArF NA=1.35 (72nm). However these patterns can be separated by a combination of innovative SMO for less than optical resolution limit and a process trick of hole-repair technique. An example of triple patterning coloring is shown in Fig 3. Fin and local interconnect are created by lines and trims. The number of trim patterns are 3 times (min. pitch=90nm) and twice (min. pitch=120nm), respectively. The small number of masks, large pitches, and simple patterns of trims come from the simple 1D layout design.
Experimental demonstration of these cut layers using design optimization, OPC-Lite, and conventional illuminators at the 7nm node dimensions will be presented. Lines were patterned with 193nm immersion with no complex OPC. The final line dimensions (22nm pitch) were achieved with pitch division 4.[5]
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