Nanoimprint lithography (NIL) is a promising technology on next generation lithography for the fabrication of semiconductor devices. NIL is a one-to-one lithographic technology with a contact transfer methodology using templates. Therefore, critical dimension (CD) error and defect performance of templates has direct impact on wafer performance. The previous paper reported that the self-aligned double patterning (SADP) process on master template had better performance on resolution and defect performance [2]. In proceeding with development of SADP template process technology, we found that CD errors occurred in the area with a pattern density change. CD control over any pattern density is one of the critical issues. In this report, we have investigated the impact of the proximity effect correction (PEC) and fogging effect correction (FEC) parameters for electron beam writing on gap space and core space. It was found that the optimal PEC parameter for resist CD is not the best for the core space and the gap space. The resist CD is uniform, but there is a difference in resist shape on the local pattern density variation. It was also found that the core space had dependency on global pattern density even if the optimal FEC parameter for resist CD was applied. FEC can correct resist CD, but it cannot adjust resist shape. By using the optimal PEC and FEC parameters for SADP process, the gap space range of 0.6 nm and the core space range of 0.5 nm were successfully obtained.
We report on the reduction of the mask 3D effect in an etched 40-pair multilayer extreme ultraviolet (EUV) lithography mask by measuring the printed ΔCD (horizontal–vertical) on exposure with a high-NA small field exposure tool (HSFET). We compared these patterns with those of a conventional Ta-based absorber EUV lithography mask. Next, we examined the programmed pattern defect printability of the etched 40-pair multilayer EUV lithography mask and showed that defect printability of the etched multilayer mask was hardly influenced by the direction of EUV illumination. We conclude that the mask 3D effect reduction contributes to simple specifications of the mask pattern defect printability in EUV lithography.
In EIDEC, a micro extreme UV (EUV) exposure tool for next-generation lithography has been developed, referred to as a High NA Small Field Exposure Tool (HSFET), and its basic configuration is as follows: Xe DPP source, critical illumination configuration, a rotationally moving turret with several sigma apertures, a larger than 30 × 200 μm field size, and variable NA mechanics to cover from 0.3 to 0.5 NA and beyond. The PO optical performance is well suited to our required 11 nm half-pitch patterning. The transmitted optical wavefront error (WFE) was measured and confirmed to be 0.29 nm RMS, which is far less than the required value of 0.6 nm RMS, and the tool was successfully installed in August 2015. Here we show the exposure results using a newly designed reticle for HSFET patterning. We report the basic printing performance and consideration for high-NA effects as know n polarization effects.
Due to the promising development status of EUVL as a practical lithography technology for the 2x-nm node, we are
continuing to evaluate its process liability using the EUV1 at Selete, which has an Off-Axis illumination capability. The
resolution limit of the EUV1 for L&S patterns is currently 18 nm for dipole illumination, and 16 nm for aggressive
dipole illumination. This study examined the critical points of EUVL for device manufacturing through wafer processes.
The yield obtained from electrical measurements indicates the maturity of the technology, including the resist process,
the tool, and the mask. Optimization of the resist and RIE processes significantly improved the yield. The final yields
obtained from electrical measurements were 100% for hp 30 nm, 70% for hp 28 nm, and 40% for hp 26 nm. These
results demonstrate EUV lithography to be a practical technology that is now suitable for 2x nm semiconductor
manufacture.
A high-resolution EUV exposure tool is needed to facilitate the development of EUV resists and masks. Since the
EUV small-field exposure tool (SFET) has a high numerical aperture (NA = 0.3), low aberration & flare, and excellent
stage stability, it should be able to resolve fine L/S patterns for the half-pitch 22-nm & 16-nm nodes. In this study, we
evaluated the resolution capability of the SFET and obtained 22-nm L/S patterns with x-slit illumination and clear
modulation of 16-nm L/S patterns with x-dipole illumination. The resolution limit of the SFET seems to be about 15 nm.
The main cause of pattern degradation in 16-nm L/S is probably resist blur. To obtain good shapes for this pattern size,
the resist blur of less than 3.5 nm (σ) is required. The use of y-slit illumination was found to reduce the linewidth
roughness (LWR) of resist patterns. Further reduction of the LWR requires a higher image contrast and a smaller flare.
Due to the central obscuration, the image contrast of the SFET is sensitive to the change of pupil fill. The degradation in
the collector & DMT should be reduced to ensure stable aerial images. This work was supported in part by NEDO.
In the fabrication of interconnect test chips with a half pitch of 35 nm, we used an EUV full-field scanner (EUV1)
for three critical layers: Metal 1, Via 1 and Metal 2. In this study, we focused on the Via-1 layer and investigated the
printing characteristics of 35-nm via-hole patterns. There are three types of major via-hole patterns; aligned, staggered,
and isolated. Simple optical proximity effect correction (OPC) and shadowing effect correction (SEC) were applied to
the mask patterns to reduce the iso-dense bias and anisotropy of hole shapes. Mask critical-dimension (CD) correction
enabled the fabrication of all three types of patterns with almost the same CD. A simulation analysis revealed the mask
error enhancement factor (MEEF) to be about 2.5, the exposure latitude to be about 18%, and the depth of focus (DOF)
to be about 100 nm for 35-nm via holes when the resist CD was 35 nm. The experimental results agree fairly well with
the simulation results. The intra-field CD uniformity of 35-nm via holes is 3.3 nm (3σ). The intra-field overlay accuracy
(Mean+3σ) between the Via-1 and Metal-2 layers is better than 15 nm. We used a multi-stacked resist to fabricate 35-nm
via holes in a low-k dielectric layer. Moreover, we fabricated interconnect test chips and measured their electrical
properties. The resistance of 32-nm vias is 12.4Ω, which meets the target of International Technology Roadmap for
Semiconductors (ITRS). The yield of 40k dense via chains was over 70%. The results demonstrate that EUV lithography
is useful for the fabrication of ULSI devices with a half pitch of 35 nm and beyond.
Extreme ultraviolet lithography (EUVL) is the most promising candidate for the manufacture of devices with a half pitch
of 32 nm and beyond. We are now evaluating the process liability of EUVL in view of the current status of lithography
technology development. In a previous study, we demonstrated the feasibility of manufacturing 32-nm-node devices by
means of a wafer process that employed the EUV1, a full-field step-and-scan exposure tool. To evaluate yield, a test
pattern was drawn on a multilayer resist and exposed. After development, the pattern was replicated in SiO2 film by
etching, and metal wires were formed by a damascene process. Resolution enhancement is needed to advance to the 22-
nm node and beyond, and a practical solution is off-axis illumination (OAI). This paper presents the results of a study on
yield improvement that used a 32-nm-node test chip, and also clarifies a critical issue in the use of EUVL in a wafer
process for device manufacture at the 22-nm node and beyond.
The Selete full-field EUV exposure tool, EUV1, manufactured by Nikon, is being set up at Selete. Its lithographic performance was evaluated in exposure experiments with a static slit using line-and-space (L&S) patterns, Selete Standard Resist 03 (SSR3), a numerical aperture of 0.25, and conventional illumination (=0.8). The results show that 25-nm L&S patterns were resolved. Dynamic exposure experiments demonstrate that the resolution is 45 nm across the exposure field. The CD uniformity across a shot is 3 nm. Evaluation of the overlay performance of the EUV1 using alignment marks on a processed wafer revealed the repeatability to be better than 1 nm. The overlay accuracy obtained with enhanced global alignment was less than 4 nm (3) after linear correction. These results show that the EUV1 has attained the quality level of a typical alpha-level lithography tool and is suitable for test site verification.
The source collector module (SoCoMo) for the extreme ultraviolet (EUV) small-field exposure tool (SFET) had been
operated for 1,700,000,000 pulse radiations using more than 20 electrodes, four debris mitigation tools (DMT), and three
collector mirrors. After 600 million pulse radiations, it was found that the EUV light intensity at wafer plane had been
decreased to less than 10% of the initial value and the pupilgram exposed by SFET had been drastically deteriorated. In
order to study on the cause of the intensity reduction and to maintain the intensity highly, three new evaluation tools
were introduced; collector position monitors, an intermediate focus (IF) spot position monitor, and an attachment of
screen tool. Utilizing these tools, it was clarified that the main causes of EUV light intensity reduction at IF plane were
the plasma fluctuation with electrode erosion, the degradation of DMT's optical transmissivity, and the degradation of
collection efficiency. These results indicated that it would be necessary for future SoCoMo not only to achieve highpower,
stable and long-life performance, but also to equip with the functions that these tools provided in order to
maximize its own performance.
Since the k1 factor is much larger in extreme-ultraviolet lithography (EUVL) than in optical lithography, optical
proximity correction (OPC) should be much simpler for patterns on EUVL masks than for those on advanced
photomasks. This will facilitate the fabrication of complex device patterns with EUVL. In this study, static
random-access memory (SRAM) cell patterns for the half-pitch (hp) 32- and 45-nm nodes were fabricated using two
EUV exposure tools (SFET, EUV1), and their fidelity was evaluated. The levels of SRAM patterns were isolation, gate,
contact, and metal. The size of the SRAM unit cell was 0.191 μm2 for the hp 45-nm and 0.097 μm2 for the hp 32-nm
patterns. Most of the experiments employed SSR2, a high-resolution EUV resist. The high performance of the SFET and
SSR2 enabled hp 45-nm SRAM patterns to be fabricated faithfully. However, some of the hp 32-nm patterns deviated
from the mask patterns. To determine the causes of this degradation, we made a simulation analysis using the Sentaurus
Lithography simulator. The main cause of the degradation was found to be resist blur. When we used MET-2D resist,
which has a relatively large resist blur, the degradation became quite severe. Although the resist blur for SSR2 is about
10 nm, it is not small enough for the hp 32-nm SRAM patterns, especially for the gate and metal levels. It is necessary to
reduce resist blur to improve the fidelity for this pattern size. Simulation results indicated that resist blur should be
reduced to about 5 nm for hp 22-nm node device patterns.
The Selete full-field EUV exposure tool, the EUV1, was manufactured by Nikon and is being set up at Selete. Its
lithographic performance was evaluated in exposure experiments with a static slit using line-&-space (L&S) patterns,
Selete Standard Resist 03 (SSR3), an NA of 0.25, and conventional illumination (σ = 0.8). The results showed that 25-
nm L&S patterns were resolved. Dynamic exposure experiments showed the resolution to be 45 nm across the exposure
field and the CD uniformity across a shot to be 3 nm, also 26-nm L&S patterns were resolved.
Overlay performance of the EUV1 was showed as processed wafer mark alignment, the repeatability was under 1nm.
Overlay accuracy using EGA (Enhanced Global Alignment) was below 4nm at the 3-sigma after liner correction. These
results were good enough for an alpha-level lithography tool and test site verification.
The effects of aberration and flare on the lithographic performance of the EUV small-field exposure tool (SFET)
were evaluated. Simulation results indicated that the effect of aberration on the image contrast of line-and-space (L&S)
patterns should be small. In exposure experiments, 26-45-nm L&S patterns were successfully fabricated under annular
illumination (σ=0.3/0.7). A key factor limiting resolution should be resist performance. Simulation results also indicated
that the astigmatic aberration could produce a focal shift of about 60 nm between horizontal and vertical L&S patterns.
The experimentally obtained focus shift agreed well with the simulation results. Dense 32-45-nm contact-hole (C/H)
patterns were also successfully fabricated under annular illumination (σ=0.3/0.5). Due to astigmatic aberration, the C/H
patterns were deformed at defocused positions, but they were almost circular at the best focus position. The flare of the
projection optics measured by the Kirk method was 11% over a flare range of 1-100 μm. The effects of the 11% flare
were evaluated using dark- and bright-field 32-nm L&S patterns. It was found that the top loss and line-width roughness
(LWR) of the resist were larger for bright-field than for dark-field patterns. To reduce the impact of flare, we need EUV
resists that are more robust with regard to flare. A comparison of the measured point spread function (PSF) of the flare
and the calculated PSF revealed good agreement for long-range flare but some difference for short-range flare.
We have installed a small-field exposure tool (SFET) manufactured by Canon and EUVA with a discharge-producedplasma
EUV source that employs Xenon gas. We investigated how the performance of the source affects lithographic
performance. Electrode life has relation to the illumination uniformity of the exposure field on wafer surface. Also
source power at the wafer surface has relation to the electrode life. Electrode life makes EUV power decreasing and
larger illumination uniformity number. We examine the pupilgram test using high sensitivity resist. Actual pupil fill
shape was observed and there was non-uniform distribution. Pupil fill shape was changed after exchanging electrode,
also resist CD bias between parallel and horizontal line of the field. That was comparable to the simulation result.
The source electrode requires periodic replacement, which impacts not only the performance of the source, but also the
lithographic performance of the tool, such as the CD of resist patterns.
KEYWORDS: Vestigial sideband modulation, Data conversion, Metals, Electron beams, Databases, Front end of line, Back end of line, Electron beam direct write lithography, Lithography, Logic devices
The EBIS data conversion system has been developed to be optimized for layout data of logic devices with Character Projection (CP) method. In the system, standard cells and memory cells are registered into a character database as keeping the hierarchy of cell pattern in the device pattern, so that a common CP aperture can be created for several logic devices. The order of EB shots are optimized to shorten the time of writing the patterns, small shots (sliver shots) create as few as possible, and the total number of EB shots are minimized for a specified CP aperture. The system was evaluated by processing ASIC devices of hp 180 nm, 130 nm and 90 nm nodes. The average processing time is about 1 hour with the average number of EB shots of 50 × 106 per a chip. The reduction rates of the number of shots from only conventional Variably Shaped Beam (VSB) to with CP were estimated about 80%, 45%, and 80% for the layers of front-end-of-line (FEOL), metal and via layers of back-end-of-line (BEOL), respectively.
KEYWORDS: Semiconducting wafers, Metals, Backscatter, Electron beam lithography, Copper, Lithography, Electron beam direct write lithography, Monte Carlo methods, Critical dimension metrology, Tungsten
Direct write electron-beam (e-beam) lithography, which has the maskless patterning capability and the quick turnaround for new device designs and design changes, has been applied to making the engineering samples for the development of the System on Chip products (SoC). Using the e-beam lithography to the multilevel interconnect metal was known to be evaluate in view of cost and throughput. In the case of the high-energy e-beam lithography, however, the backscattered electron from the metal caused a significant proximity effect.
Authors evaluated the e-beam proximity effect using the accelerating voltage 50keV on some multi-level interconnect metal structures which consist in tungsten wiring, or Cu wiring. It was found that the backscattering range and the ratio of the backscattering energy to the incident energy depend on the thickness of metal, but also on the distance from the resist to the metal.
Therefore authors propose a new method of evaluating e-beam lithography property, concept of "EB-tree". That indicates the wafer backscatter property that has heavy metal wiring using e-beam lithography. EB-tree shows the relations of wafer backscatter range and heavy metal thickness, ratio of the backscattering energy and heavy metal thickness. EB-tree could show wafer property cause of lower levels layout, understructure metal wiring, that must be taken into account when e-beam lithography.
In the application of the high-energy electron-beam (e-beam) lithogrpahy to the multi-level interconnect metal; the backscattered electron from the heavy metal previously patterned in lower levels on the substrate causes a significant proximity effect. We estimated the "inter-level" proximity effect in the e-beam exposure with the accelerating voltage of 50kV on some multi-level interconnect metal structures which consist in aluminum wiring and tungsten plugs. It was found that the backscattering range and the backscattering energy ratio to the incident energy depend not only on the density and thickness of metal but also on the distance between the resist and the heavy metal plugs. In this paper, a novel proximity effect correction algorithm is proposed, where the exposing patterns are divided into some classes according to the metal structure, the total backscattering energy deposited in the resist is expressed by the sum of the backscattering energy from each structural class, and the exposrue dose is modulated by the function of the total backscattering energy.
KEYWORDS: Back end of line, Vestigial sideband modulation, Logic devices, Metals, Data processing, Photomasks, Electron beams, Electron beam direct write lithography, Computer aided design, Beam shaping
Electron beam direct writing (EBDW) system is at the head of systems fabricating circuit patterns by maskless. But the throughput of EBDW is very poor beause very large number of electron beam (EB) shots are requested for exposure of whole patterns on a wafer. We had proposed methods of reduction of the number of EB shots with Character Projection (CP) and designing the best devicve pattern for CP-EBDW to fabricate logic devices such as ASIC or SoC device. Though the method is effective to Front-End-Of-Line (FEOL) layers of cell based logic deviec, Back-End-Of-Line (BEOL) layers cannot be exposed by the method with small number of characters and EB shots. Now, we will propose methods for appropriate CP exposure and data processign for patterns in BEOL layers. By the methods, each BEOL layer in a typical logic device cna be exposed with throughputs about 6 to 8 wafers/h, with a Low-energy-EBDW system produced by e-BEAM Corporation, named "EBIS".
KEYWORDS: Critical dimension metrology, Photomasks, Lithography, Scattering, Laser systems engineering, Control systems, Laser scattering, Monte Carlo methods, Beam controllers, Diffusion
When making photomasks for low-k1 lithography, critical dimension (CD) control is more important than pattern resolution on the photomask. Photomasks are written by an electron-beam (EB) writing system or a laser beam writing system. A high-acceleration-voltage EB writing system that has less beam blue is now expected to be a useful tool for fabricating photomasks with accurate CD control. To clarify the latitudes of dose accuracy and beam blue for photomasks of under 0.15 micrometers lithography, we studied Cd controllability for with dose fluctuation respect to beam blue and resist thickness using a 50 kV acceleration voltage EB writing system. The CD variation rate with does fluctuation strongly depends on pattern density, beam blue and resist thickness. The CD variation rate decreases with decreasing beam blur. Thinner resists, especially, are effective for improving CD control when beam blue is small enough. However, when beam blur is 70 nm, the effect of thinner resists in controlling CD is less because the origin of deposited energy blur is primarily the beam blur. To realize CD control within 10 nm, +/- -3 dose accuracy, 40 nm beam blur, and 30 nm resist thickness are necessary.
We have developed a new method of preparing pattern data to increase throughput of an EB writing system. The main idea is to expand cells smaller than a threshold size to the corresponding upper level cells during hierarchical shape data operations, which leads to reduction of the number of subfields and shots in our EB writing system. The cell expansions, however, could cause increase in the data volume and data conversion time as a result of destroying the hierarchy of CAD data. Therefore, we have introduced an additional rule, that is, not to expand cell arrays which have more elements than a threshold number. The new data conversion processor, which adopts the above-mentioned cell expansion algorithm, has been applied to a 64Mbit and a 256Mbit DRAM. The new module was applied to three layers, that is, the trench layer, the gate poly layer and metal layer of each DRAM. As a result, we found that the number of subfields and the number of shots were reduced by about 60% and 35%, respectively, for the average of 6 layers. Resulting throughput was evaluated as 1.8 times for the average of 6 layers. Performance change in the conversion processor has been examined in terms of data volume and data conversion time, and is discussed in the paper.
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