In this study we investigated the influence of the deposition technique on the surface topology and the resulting device performance in organic thin film transistors (OTFT). We varied the parameters of flexographic and gravure printing for the organic semiconductor (OSC) and did multilayer gravure printing for the dielectric, respectively. Therefore, we manufactured transistors in bottom contact top gate architecture and compared them to spin coated samples. As investigation tool for OTFTs, the charge carrier velocity distribution is correlated with the optical characteristics of the printed layers. We found a dependency of the printing technique on the surface topology of the semiconductor and, due to the resulting increase of the channel length, a broadening of the charge carrier velocity distribution. For the dielectric we found a dependency on the layer thickness which seems to be independent from the deposition technique.
For the development of circuits consisting of organic thin film transistors (OTFT) with satisfying yield, a stable and reliable process is necessary. This can be achieved by eliminating failure mechanisms and understanding the charge transport phenomena in the individual device. Following the way of a charge through the device, we start with the investigation of the influence of the Schottky barrier height and contact morphology on the device performance by finite-elements simulations. It could be verified that the charge injection limiting contact resistance can be decreased by two orders of magnitude by reducing the thin oxide layer at the source and drain contacts and improving the semiconductor layer morphology at their vicinity. Second, we present an analytical closed-form solution of the OTFT channel potential used for Monte-Carlo charge transport simulations and compute current-voltage and transient response characteristics out of it. In a next step, the influence of the deposition process on the layer interface is investigated. Therefore, velocity distribution measurements of the charge carriers lead to a simulation model with varying disorder, depending on the layer surfaces and deposition techniques. Afterwards, leakage currents through the gate dielectric can be described by a poor conducting semiconductor model in the finite-elements framework. Leakage currents increase power consumption in circuits and, what is more critical, can lead to a total failure of the OTFT. However, they can be influenced by the number of deposited dielectric layers and charge injection supporting self-assembled monolayers at the source and drain contacts. These findings lead to circuit building blocks for an organic device library whereupon still existing performance fluctuations can be coped with Monte-Carlo circuit simulations.
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