EUV lithography continues to make scaling cost effective for chip manufacturers and allows Moore`s law to pursue. High NA EUV with its increased numerical aperture (NA) from 0.33NA to 0.55NA enables 1.7x smaller features and improved local CDU. This brings several benefits for advance chipmakers such as patterning cost reduction due to multi-patterning, reduced defect density as a result of process simplification and shorter cycle time via mask reduction. Currently, there are multiple high NA EUV systems (EXE:5000) which completed the built and qualification in the ASML factory. The first performance data is being collected via one of these high NA EUV systems. This paper will cover the performance results of the high NA EUV platform (EXE:5000) on imaging and overlay based on the initial findings from common learning collaboration. Furthermore, the progresses towards future high NA EUV systems will be described.
Multi-wavelength (MWL) micro diffraction-based overlay (μDBO) is a prominent method for after-develop inspection (ADI) overlay measurements, which is favorable for accuracy and robustness. Continuous-bias DBO (cDBO) is expected to offer robustness improvements against stack variation, asymmetry, and imbalance. In this paper, dual-WL (DWL) cDBO profiles were evaluated to secure the advantages of both of MWL and cDBO applications. The metrics used to evaluate accuracy and robustness of ADI overlay measurements are residual, dynamic precision (DP), and wafer-to-wafer variation of the difference between ADI and after-etch inspection overlay. 70% of DWL profiles had improvements in their residual values comparing with their single-WL (SWL) constituents on Samsung R&D wafers in layer A. On layer B, the best DWL cDBO profiles showed around 5% improved residuals comparing with its SWL constituents. DWL cDBO showed around 30% averaged improved DP compared with SWL counterparts. DP improvements of MWL cDBO are following the expected DP improvements, based on the signal-to-noise ratio improvement with increasing number of signals. Residual improvement with increasing number of WLs is different from the DP improvement, and the best DWL residual improvement is higher than that of SWL measurements with noise reduction techniques applied. This shows that the residual improvement cannot be attributed to the increased number of acquisitions, and that it could be an innate advantage of MWL cDBO.
In this paper the use of the EPE metric directly in the process optimization method for a DRAM use case has been researched. We show that EPE-aware optimization, using scanner dose and overlay control sub-recipes, is outperforming conventional optimization in terms of EPE Dies in Spec. Hence, it can be expected that also device yield can be improved by EPE-aware control.
During metrology overlay recipe setup typically a wide range of different target designs are present to select from. The main goal of recipe setup is to select the most accurate target type-recipe combination at ADI (after develop inspection) without additional external information that can be used for production on a large set of wafers. We will introduce a method based on blind source separation to disentangle the contributions of target asymmetry and the overlay of the targets. Based on this separation, the most accurate target-recipe combination can be selected. On top of selecting the most accurate target-recipe combination, it is important to stabilize the difference between the overlay on device and the overlay as measured on the target. In order to increase that stability we will introduce advanced algorithms in the ADI measurements that use measured asymmetry parameters to correct for inline target asymmetry variation. We will show a metrology to device matching improvement of up to 40% on product wafers.
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