Mr. Steven Tottewitz Profile

Steven Tottewitz

Staff process engineer at Qoniac GmbH

Area of Expertise:

Lithography Engineer

Websites:

Company Website

Publications (7)

Proceedings Article | 20 March 2020 Paper

High-order field distortion correction using standalone alignment technology with modeling and sampling optimization

Takehisa Yahiro, Katsushi Makino, Haruki Saito, Steven Tottewitz, Boris Habets, Patrick Lomtscher, Jiro Hanaue

Proceedings Volume 11325, 113251Y (2020) https://doi.org/10.1117/12.2551603

KEYWORDS: Distortion, Semiconducting wafers, Optical alignment, Optimization (mathematics), Scanners, Overlay metrology, Process control, Reticles, Data modeling

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Proceedings Article | 26 March 2019 Paper

Intra-field alignment for overlay feed-forward simulation with sampling optimization

Cheng Hao Yang, Chun Chi Yu, Patrick Lomtscher, Martin Freitag, Steven Tottewitz, Boris Habets, Hsiao Lin Hsu, Rex Liu

Proceedings Volume 10959, 109592T (2019) https://doi.org/10.1117/12.2514984

KEYWORDS: Semiconducting wafers, Optical alignment, Data modeling, Overlay metrology, Data corrections, Visualization, Lithography, Reticles, Optimization (mathematics)

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Proceedings Article | 26 March 2019 Paper

Overlay run-to-run control based on device structure measured overlay in DRAM HVM

Hsiao Lun Chu, Foster Huang, Steven Tottewitz, Boris Habets, Patrick Lomtscher, Hsiao-Lin Hsu, Afu Chiu, Rex Liu

Proceedings Volume 10959, 109592P (2019) https://doi.org/10.1117/12.2515203

KEYWORDS: Overlay metrology, Etching, Device simulation, Feedback control, Lithography, Measurement devices, Semiconducting wafers, Control systems, High volume manufacturing, Inspection

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In leading edge lithography, overlay is usually controlled by feedback based on measurements on overlay targets, which are located between the dies. These measurements are done directly after developing the wafer. However, it is well-known that the measurement on the overlay marks does not always represent the actual device overlay correctly. This can be due to different factors, including mask writing errors, target-to-device differences and non-litho processing effects, for instance by the etch process.¹

In order to verify these differences, overlay measurements are regularly done after the final etch process. These post-etch overlay measurements can be performed by using the same overlay targets used in post-litho overlay measurement or other targets. Alternatively, they can be in-device measurements using electron beam measurement tools (for instance CD-SEM). The difference is calculated between the standard post-litho measurement and the post-etch measurement. The calculation result is known as litho-etch overlay bias.

This study focuses on the feasibility of post-etch overlay measurement run-to-run (R2R) feedback instead of post-lithography R2R feedback correction. It is known that the post-litho processes have strong non-linear influences on the in-device overlay signature and, hence, on the final overlay budget. A post-etch based R2R correction is able to mitigate such influences.²

This paper addresses several questions and challenges related to post-etch overlay measurement with respect to R2R feedback control. The behavior of the overlay targets in the scribe-line is compared to the overlay behavior of device structures. The influence of different measurement methodologies (optical image-based overlay vs. electron microscope overlay measurement) was evaluated. Scribe-line standard overlay targets will be measured with electron microscope measurement. In addition, the influence of the intra-field location of the targets on device-to-target shifts was evaluated.

Proceedings Article | 13 March 2018 Presentation + Paper

Understanding overlay signatures using machine learning on non-lithography context information

Marshall Overcast, Corey Mellegaard, David Daniel, Boris Habets, Georg Erley, Steffen Guhlemann, Xaver Thrun, Stefan Buhl, Steven Tottewitz

Proceedings Volume 10585, 105851U (2018) https://doi.org/10.1117/12.2303487

KEYWORDS: Semiconducting wafers, Overlay metrology, Etching, Machine learning, Optical alignment, Error analysis, Metrology, Lithography, Data processing, Semiconductors

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Proceedings Article | 13 March 2018 Paper

Higher order intra-field alignment for intra-wafer lens and reticle heating control

Charlie Chen, En-Chuan Lio, Hsiao Lin Hsu, Jia Hung Chang, Sho Shen Lee, Patrick Lomtscher, Boris Habets, Georg Erley, Norman Birnstein, Steven Tottewitz, Rex Liu

Proceedings Volume 10585, 105851R (2018) https://doi.org/10.1117/12.2297358

KEYWORDS: Optical alignment, Semiconducting wafers, Reticles, Overlay metrology, Data modeling, Neodymium, HVAC controls, Distortion, Calibration, Roads

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Proceedings Article | 28 March 2017 Presentation + Paper

Topography based wafer clustering for wafer level overlay correction

Hongoo Lee, Sangjun Han, Heongsoo Kim, Boris Habets, Enrico Bellmann, Steven Tottewitz, Stefan Buhl, Martin Rößiger, Seop Kim

Proceedings Volume 10145, 101450Q (2017) https://doi.org/10.1117/12.2259858

KEYWORDS: Semiconducting wafers, Overlay metrology, Molybdenum, Optical alignment, Lithography, Etching, Deposition processes, Distortion, Data modeling, Computer simulations

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Proceedings Article | 19 March 2015 Paper

Overlay improvement using Legendre-Zernike model-based overlay corrections and monitoring with interpolated metric

Md Zakir Ullah, Rajanish Javvaji, Alan Lim, Lieu Chia Chuen, Boris Habets, Stefan Buhl, Georg Erley, Steven Tottewitz, Enrico Bellmann

Proceedings Volume 9424, 942420 (2015) https://doi.org/10.1117/12.2085013

KEYWORDS: Semiconducting wafers, Data modeling, Overlay metrology, Performance modeling, Model-based design, Process modeling, Coastal modeling, Zernike polynomials, Process control, Semiconductors

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Showing 5 of 7 publications

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