Dr. Teresa Riesgo Profile

Dr. Teresa Riesgo

Professor at Univ Politécnica de Madrid

SPIE Involvement:

Author | Editor

Publications (14)

Proceedings Article | 11 March 2015 Paper

Paper

Performance evaluation for different sensing surface of BICELLs bio-transducers for dry eye biomarkers

M. Laguna, M. Holgado, B. Santamaría, A. López, M. Maigler, A. Lavín, J. de Vicente, J. Soria, T. Suarez, C. Bardina, M. Jara, F. Sanza, R. Casquel, A. Otón, T. Riesgo

Proceedings Volume 9337, 93370J (2015) https://doi.org/10.1117/12.2077174

KEYWORDS: Eye, Biosensing, Adsorption, Biomedical optics, Point-of-care devices, Transducers, Fabry–Perot interferometry, Sensing systems, Reflectivity, Adaptive optics

Read Abstract +

Proceedings Article | 28 May 2013 Paper

Paper

High speed Radix-4 soft-decision Viterbi decoder for MB-OFDM UWB system

Guixuan Liang, Jorge Portilla, Teresa Riesgo

Proceedings Volume 8764, 87640F (2013) https://doi.org/10.1117/12.2017621

KEYWORDS: Clocks, Signal processing, Field programmable gate arrays, Distance measurement, Orthogonal frequency division multiplexing, Algorithm development, Forward error correction, Logic, CMOS technology, Wireless communications

Read Abstract +

Proceedings Article | 28 May 2013 Paper

Paper

Hardening digital systems with distributed functionality: robust networks

Anna Vaskova, Marta Portela-Garcia, Mario Garcia-Valderas, Celia López-Ongil, Jorge Portilla, Juan Valverde, Eduardo de la Torre, Teresa Riesgo

Proceedings Volume 8764, 87640L (2013) https://doi.org/10.1117/12.2017474

KEYWORDS: Sensors, Sensor networks, Distributed computing, Tolerancing, Data processing, Data acquisition, Reliability, Chemical elements, Field programmable gate arrays, Humidity

Read Abstract +

Proceedings Article | 28 May 2013 Paper

Paper

Architectural evaluation of dynamic and partial reconfigurable systems designed with DREAMS tool

Andrés Otero, Ángel Gallego, Eduardo de la Torre, Teresa Riesgo

Proceedings Volume 8764, 87640H (2013) https://doi.org/10.1117/12.2021271

KEYWORDS: Computer aided design, Logic, Human-machine interfaces, Telecommunications, Field programmable gate arrays, Visualization, Virtual reality, Clocks, Manufacturing, Computer architecture

Read Abstract +

Proceedings Article | 3 May 2011 Paper

Paper

Bio-inspired FPGA architecture for self-calibration of an image compression core based on wavelet transforms in embedded systems

Rubén Salvador, Alberto Vidal, Félix Moreno, Teresa Riesgo, Lukáš Sekanina

Proceedings Volume 8067, 806704 (2011) https://doi.org/10.1117/12.887123

KEYWORDS: Wavelets, Image compression, Discrete wavelet transforms, Image processing, Field programmable gate arrays, Calibration, Evolutionary algorithms, Embedded systems, Wavelet transforms, Image filtering

Read Abstract +

Proceedings Article | 3 May 2011 Paper

Paper

Scalable 2D architecture for H.264 SVC deblocking filter with reconfiguration capabilities for on-demand adaptation

T. Cervero, A. Otero, E. de la Torre, S. López, G. Callicó, T. Riesgo, R. Sarmiento

Proceedings Volume 8067, 80670K (2011) https://doi.org/10.1117/12.887951

KEYWORDS: Scalable video coding, Field programmable gate arrays, Clocks, Video, Standards development, Electroluminescence, Neodymium, Image processing, Chemical elements, Computer programming

Read Abstract +

Proceedings Article | 3 May 2011 Paper

Paper

Cost and energy efficient reconfigurable embedded platform using Spartan-6 FPGAs

A. Otero, M. Llinás, M. Lombardo, Jorge Portilla, E. de la Torre, T. Riesgo

Proceedings Volume 8067, 806706 (2011) https://doi.org/10.1117/12.887498

KEYWORDS: Field programmable gate arrays, Logic, Clocks, Error control coding, Control systems, Embedded systems, Sensor networks, Digital signal processing, Chemical elements, Manufacturing

Read Abstract +

Proceedings Article | 3 May 2011 Paper

Paper

SCA security verification on wireless sensor network node

Wei He, Carlos Pizarro, Eduardo de la Torre, Jorge Portilla, Teresa Riesgo

Proceedings Volume 8067, 80670W (2011) https://doi.org/10.1117/12.887537

KEYWORDS: Sensor networks, Information security, Network security, Antennas, Electromagnetism, Field programmable gate arrays, Detection and tracking algorithms, Mathematics, Computer security, Capacitors

Read Abstract +

Proceedings Article | 3 May 2011 Paper

Paper

Low-power, high-speed FFT processor for MB-OFDM UWB application

Guixuan Liang, Danping He, Eduardo de la Torre, Teresa Riesgo

Proceedings Volume 8067, 80670E (2011) https://doi.org/10.1117/12.890303

KEYWORDS: CMOS technology, Clocks, Binary data, Orthogonal frequency division multiplexing, Algorithm development, Signal processing, Control systems, Signal to noise ratio, Quantum efficiency, Wireless communications

Read Abstract +

Proceedings Article | 28 May 2009 Paper

Paper

NoC generation of an optimal memory distribution for multimedia systems

Raúl Regidor, Félix Tobajas, Valentin de Armas, Eduardo de la Torre, Teresa Riesgo, Roberto Sarmiento

Proceedings Volume 7363, 73630P (2009) https://doi.org/10.1117/12.821523

KEYWORDS: Network on a chip, Multimedia, Telecommunications, Networks, Video processing, System on a chip, Process modeling, Digital signal processing, Modeling, Video

Read Abstract +

Proceedings Article | 28 May 2009 Paper

Paper

Approach to an FPGA embedded, autonomous object recognition system: run-time learning and adaptation

Rubén Salvador, Carlos Terleira, Félix Moreno, Teresa Riesgo

Proceedings Volume 7363, 736312 (2009) https://doi.org/10.1117/12.821687

KEYWORDS: Object recognition, Field programmable gate arrays, Neural networks, Computer architecture, Very large scale integration, Current controlled current source, Pattern recognition, Network security, Control systems, Network architectures

Read Abstract +

Proceedings Article | 28 May 2009 Paper

Paper

Method for run time hardware code profiling for algorithm acceleration

Vladimir Matev, Eduardo de la Torre, Teresa Riesgo

Proceedings Volume 7363, 736304 (2009) https://doi.org/10.1117/12.821704

KEYWORDS: Field programmable gate arrays, Profiling, Control systems, Detection and tracking algorithms, Multimedia, Sensors, Telecommunications, Clocks, Logic, Video

Read Abstract +

Proceedings Article | 10 May 2007 Paper

Paper

High-level power estimation for digital system

Yaseer Durrani, Ana Abril, Teresa Riesgo

Proceedings Volume 6590, 659002 (2007) https://doi.org/10.1117/12.721182

KEYWORDS: Monte Carlo methods, Tin, Statistical analysis, Error analysis, Switching, Genetic algorithms, Intellectual property, Telecommunications, Electronic design automation, Device simulation

Read Abstract +

Proceedings Article | 10 May 2007 Paper

Paper

Integrated hardware interfaces for modular sensor networks

J. Portilla, A. de Castro, A. Abril, T. Riesgo

Proceedings Volume 6590, 659014 (2007) https://doi.org/10.1117/12.723773

KEYWORDS: Sensors, Transducers, Sensor networks, Actuators, Field programmable gate arrays, Analog electronics, Clocks, Rapid manufacturing, Signal processing, Temperature sensors

Read Abstract +

Showing 5 of 14 publications

Proceedings Volume Editor (3)

SPIE Conference Volume | 4 June 2013

VLSI Circuits and Systems VI

SPIE Conference Volume | 3 May 2011

VLSI Circuits and Systems V

SPIE Conference Volume | 18 May 2009

VLSI Circuits and Systems IV

Conference Committee Involvement (3)

VLSI Circuits and Systems VI

24 April 2013 | Grenoble, France

VLSI Circuits and Systems

18 April 2011 | Prague, Czech Republic

VLSI Circuits and Systems

4 May 2009 | Dresden, Germany

SIGN IN TO:

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Advertisement

Advertisement