A simultaneous bidirectional CMOS transceiver for full duplex chip-to-chip optical interconnects is proposed, utilizing a
resistor-transconductor (R-gm) hybrid. The hybrid separates the inbound signal from the input/output compound signal.
The simultaneous bidirectional CMOS transceiver is designed in a 0.18 μm Si-CMOS technology, with power
dissipation of 79 mW and 54.4 mW for the transmitter and receiver, respectively. It shows a 3-dB bandwidth of 4.6 GHz
for both the transmitter and the receiver with a 3-dB gain of 26.6 dB and 10.6 dB, respectively, in full-duplex mode.
KEYWORDS: Clocks, Digital electronics, Eye, Analog electronics, Transistors, Field programmable gate arrays, Field effect transistors, Optical design, Switching, Multiplexing
An analog-type high-speed serializer/deserializer (SerDes) has been designed for optical links especially between CPU
and memory. The circuit uses a system clock and its phases to multiplex data to the serial link which avoids the need for
a PLL-based high frequency clock generation used in serializing parallel data as in conventional SerDes design. The
multiplexed link combined with the de-serializing clock is used as a reference signal for de-serialization. The SerDes is
being designed in a 0.13 μm Si-CMOS technology. The fabricated serializer has a core chip size of 360 x750 μm2. Power
dissipation for the SerDes is 71.4 mW operating up to 6.5 Gbps.
A multi-channel gated-oscillator-based clock and data recovery (CDR) circuit for chip-to-chip optical link applications is
proposed and designed. The key components of the proposed CDR are a charge-pump phase-locked loop (CPPLL),
gated-oscillators, and decision circuits. The proposed multi-channel CDR has the center frequency of gated oscillator
around 2.5 GHz; however, the input data rate of each channel can be up to 3.2 Gbps. It achieves an acquisition time of 1
μs. The power dissipation is 18.27 mW for the CPPLL and 21.21 mW for each channel of the CDR. The chip size of the
CPPLL is 800×750 µm2, while that of each channel of the CDR is 200×250 μm2 in a 0.18 μm CMOS technology.
The development and testing of a new actuator for helicopter rotor control, the Double X-Frame, is described. The actuator is being developed for wind tunnel and flight testing on an MD-900 helicopter. The double X-frame actuator has a number of design innovations to improve its performance over the original X-frame design of Prechtl and Hall. First, the double X-frame design uses two X-frames operating in opposition, which allows the actuator stack preloads to be applied internally to the actuator, rather than through the actuation path. Second, the frames of the actuator have been modified to improve the actuator form factor, and increase the volume of active material in the actuator. Testing of the double X-frame piezoelectric actuator was conducted in order to determine its performance (stroke and stiffness) and robustness. In general, stiffness test data compared well with the analytical predictions. The actuator stroke was about 15% less than expected, probably due to the stack output being less in the actuator than as measured in single stack segment testing in the lab. The actuator was also tested dynamically, to determine its frequency response. Actuator robustness was evaluated by measuring its performance when subjected to the effects of blade bending, vibration, and centrifugal loading. Blade elastic bending and torsion deformations were simulated by shimming of the actuator mounts. To assess the impact of the blade vibrations, the actuator and bench test rig were mounted on a hydraulic shaker and subjected to flapwise or chordwise accelerations up to 30 g. To assess the impact of centrifugal force loading, the actuator and bench test rig were spun in the University of Maryland vacuum chamber, so that the actuator was subjected to realistic accelerations, up to 115% of nominal. Results showed that actuator output (force times stroke) was largely unaffected by dynamic and steady accelerations or elastic blade deformations.
Piezoelectric actuator technology has now reached a level where macro-positioning applications in the context of smart structures can be considered. One application with high payoffs is vibration reduction, noise reduction, and performance improvements in helicopters. Integration of piezoelectric actuators in the rotor blade is attractive, since it attacks the problem at the source. The present paper covers the development of a piezoelectric actuator for trailing edge flap control on a 34-foot diameter helicopter main rotor. The design of an actuator using bi-axial stack columns, and its bench, shake, and spin testing are described. A series of enhancements lead to an improved version that, together with use of latest stack technology, meets the requirements. Next steps in this DARPA sponsored program are development of the actuator and full scale rotor system for wind tunnel testing in the NASA Ames 40 X 80 foot wind tunnel and flight testing on the MD Explorer.
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