In this paper, we describe an integrated design space analysis approach consisting of full factorial layout
generation, lithography simulations with added proximity effects, and rigorous statistical analysis through monte-carlo
simulations which is used in the evaluating interconnects. This agile Design rule development process provides a quick
turnaround time to down-select the potential layout configurations that can offer a competitive, robust and reliable
design and manufacturing. Further layout and placement optimization is carried out to evaluate intra-cell, inter-cell and
cell boundary situations, which are critical for a place and routed block. These interconnects developed using the
integrated approach has been the key contributor to give 20-30% higher performance at the same Iddq leakage for 8T
libraries compared to Single Diffusion break or Double Diffusion break based 12T libraries in 22FDX Technology.
In order to allow competitive and low-cost designs in the 22nm FD-SOI technology 22FDX™, novel Middle-of-Line
(MOL) constructs have been specifically enabled. The Gate Tie-Down (or “continuous RX”) construct allows an optimal
device performance without loss of area. A method for a silicon-based evaluation and optimization of the Gate Tie-Down
construct is presented here. We discuss the main design-process failure modes, their severity and the risk mitigation
options. A full-factorial Design of Experiment used for the construct validation is presented and analyzed. Two critical
failure modes are isolated and discussed. As a final step, the optimized design is validated over a much larger number of
occurrences, showing a robust 4-sigma manufacturing design margin.
Monte Carlo simulations are used in the semiconductor industry to evaluate variability limits in design rule generation, commonly for interaction between different layers. The variability of the geometry analyzed is determined mainly by the lithography, process and OPC used. Monte Carlo methods for design rule evaluation can provide the requisite level of accuracy, and are suitable for two or more layer interactions because the variations on one can be assumed to be independent of variations on the other(s). The variability parameters and budget utilized in optical Monte Carlo simulations is well-established. With the upcoming implementation of EUV lithography the variability budget will be impacted. EUV has an off-axis illumination angle that complicates the lithography process by causing telecentricity and shadowing errors. Telecentricity errors manifest as a printed feature being shifted relative to the design. The amount the feature is shifted is a function of the pattern density and design. Shadowing is caused by the 3D nature of the mask combined with EUV reflective mask technology. A shadow occurs at feature edges, where the source does not fully illuminate. Telecentricity and shadowing errors, although small at the 10 nm node, will increase in relative size compared to the features printed beyond the 7 nm node. Telecentricity and shadowing errors are complex in nature and can’t be compensated for with a flat bias. These errors unique to EUV are incorporated into Monte Carlo simulations and evaluated against the standard cell design layers. The effect of these variability parameters is evaluated on critical 7 nm node layout clips.
Silicon-based electro-optic (EO) modulator is an indispensable building block for integrated lightwave circuits. In this
paper, we report an EO modulator that incorporates a heterojunction bipolar transistor (HBT) with Ge composition
graded base. The emitter is n-type doped silicon with a doping concentration of 1021/cm3. The width of the emitter strip
is 0.2μm and the thickness of the emitter layer is 0.16μm. The base has a thickness of 40nm with varying Ge
composition from zero at the emitter-base junction side to 20% at the base-collector junction side. Raised extrinsic base
is incorporated for base contact. The intrinsic base is p-type doped with a concentration of 4×1019/cm3. The HBT is
biased at VCE = 0.5 V whereas VBE is switched between -1.0V and 1.0V. The carrier distribution at "ON" state of the EO
modulator and the transient analysis are performed by MEDCI simulation. The changes of the refractive indices of the
HBT are computed from the carrier density in all regions, and then the refractive index map is imported into an optical
mode solver (RSoft BeamProp). The HBT EO modulator that supports only one optical mode is ideal, but a trade-off
between modal property and device speed is observed. For current design, we achieved a π-phase modulation length of
less than 600μm, and a switching delay less than 62ps.
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