Today novel RET solutions are gaining more and more attention from the lithography community that is facing new challenges in attempting to meet the new requirement of the SIA roadmap. Immersion, high NA, polarization, and mask topography, are becoming common place terminology as lithographers continue to explore these areas. Here with, we compare a traditional 6% MoSi based EAPSM reticle and a high transmission solution made of a SiON/Cr film stack. Insights into the manufacturability of high transmission material are provided. Test patterns have been analyzed to determine the overall impact of imaging performance when used with immersion scanners and polarized light. Some wafer results provide reliability of simulations, which are used to make further investigation on polarization and immersion effects.
Today novel RET solutions are gaining more and more attention from the lithography community that is facing new challenges in attempting to meet the new requirement of the SIA roadmap. Immersion, high NA, polarization, and mask topography, are becoming common place terminology as lithographers continue to explore these areas. Here with, we compare a traditional 6% MoSi based EAPSM reticle and a high transmission solution made of a SiON/Cr film stack. Insights into the manufacturability of high transmission material are provided. Test patterns have been analyzed to determine the overall impact of imaging performance when used with immersion scanners and polarized light. Some wafer results provide reliability of simulations, which are used to make further investigation on polarization and immersion effects.
Various types of line ends have been evaluated for either straight CPL mask or hybrid type builds. The authors will focus on image line end shortening and the impact of through dose and focus performance for very high NA ArF imaging. Simulations on test structures have been calculated along with in photoresist simulations to predict the impact on process window capability. Test structures have been designed and fabricated into a functional test for evaluation. Process evaluations have been completed and exposure-defocus window calculated.
Today the industry is filled with intensity-balanced c:PSM and much more focus is being placed on innovative approaches such as CPL (and in conjunction with IML for Contacts) and tunable transmission embedded attenuating phase shift mask (TT-EAPSM). Each approach has its own merits and demerits depending on the manufacturing strategy and lithography performance required. Currently the only commercially available photomask blanks are different chrome thickness binary and 6% attenuating blanks using molybdenum-silicide, making the accessibility to alternate transmissions much more challenging. This paper investigates the mask manufacturability of a tunable transmission embedded attenuating phase shift mask. New film materials that are used in the mask blank manufacture are modeled, deposited and characterized to determine its ability to meet performance requirements. Sputtering models, by rate and gas component, determines film stacks with tunable transmissions and thicknesses. Chemical durability, etch selectivity and thickness are a few parameters of the films that have been characterized to enhance the manufacturability and process reliability of the masks. Lithography simulation models using measured optical properties were developed and test masks that include actual device designs were fabricated. Analysis of CD variation, pattern fidelity and process margin was performed using 3D mask simulation to understand the impact on 65nm design rules. Feasibility and performance of tunable transmission photomasks for use in design and lithography are verified. Moreover, the mask manufacturability and lithography performance is compared to other enhancement techniques and their merits presented.
The requirements for critical dimension control on gate layer for high performance products are increasingly demanding. Phase shift techniques provide aerial image enhancement, which can translate into improved process window performance and greater critical dimension (CD) control if properly applied. Unfortunately, the application of hard shifter technology to production requires significant effort in layout and optical proximity correction (OPC) application. Chromeless Phase Lithography (CPL) has several advantages over complementary phase mask (c:PSM) such as use of a single mask, and lack of phase placement 'coloring' conflicts and phase imbalance issues. CPL does have implementation issues that must be resolved before it can be used in full-scale production. CPL mask designs can be approached by separating features into three zones based on several parameters, including size relative to the lithographic resolution of the stepper lens, wavelength, and illumination conditions defined. Features are placed into buckets for different treatment zones. Zone 1 features are constructed with 100% transmission phase shifted structures and Zone 3 features are chrome (binary) structures. Features that fall into Zone 2, which are too wide to be defined using the 100% transmission of pure CPL (i.e. have negative mask error factor, MEEF) are the most troublesome and can be approached in several ways.
The authors have investigated the application of zebra structures of various sizes to product type layouts. Previous work to investigate CPL using test structures set the groundwork for the more difficult task of applying CPL rules to actual random logic design layouts, which include many zone transitions. Mask making limitations have been identified that play a role in the zebra sizing that can be applied to Zone 2 features. The elimination of Zone 2 regions was also investigated in an effort to simplify the application of CPL and improve manufacturability of reticle through data enhancements.
This paper shows the capability of chromeless phase lithography (CPL) and is particularly focused on different strategies for optical proximity corrections (OPC). A chromeless phase database is easily obtained from the original layout by changing the chromium pattern into a phase pattern. However, a specific optical proximity correction has to be applied due to the phase effect and the high transmission of the mask. Mask Error Enhancement Factor (MEEF) and process window for CPL technology have been estimated through wafer exposures. Moreover, various optical proximity correction strategies have been explored through a comparison between phase and chromium features such as hammerhead, zebra and scattering bars 1,2. Indeed, depending on the density of the pattern, we can improve the contrast and the process window by changing the local transmission. The transmission can be controlled by the addition of sub resolution chromium feature such as zebra chromium transverse features on the line for dense pattern, or chromium scattering bars in the space for a sparse pattern, or chromium patches on the line end. From 65 nm node measurements and 45 nm node simulations, the authors will then present the most effective sub resolution pattern to implement.
The lithography prognosticator of the early 1980’s declared the end of optics for sub-0.5μm imaging. However, significant improvements in optics, photoresist and mask technology continued through the mercury lamp lines (436, 405 & 365nm) and into laser bands of 248nm and to 193nm. As each wavelength matured, innovative optical solutions and further improvements in photoresist technology have demonstrated that extending imaging resolution is possible thus further reducing k1. Several authors have recently discussed manufacturing imaging solutions for sub-0.3k1 and the integration challenges. The requirements stated in the ITRS roadmap for current and future technology nodes are very aggressive. Therefore, it is likely that high NA in combination with enhancement techniques will continue further for aggressive imaging solutions. Lithography and more importantly “imaging solutions” are driven by economics. The technology might be extremely innovative and “fun”, however, if it's too expensive it may never see the light of scanner. The authors have investigated and compared the capability of high transmission mask technology and image process integration for the 45nm node. However, the results will be graded in terms of design, mask manufacturability, imaging performance and overall integration within a given process flow.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET's). The race to smaller and smaller geometry's has forced device manufacturers to k1's approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.
Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/- 9nm1. Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error factor (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as contacts. We have investigated the use of CPL mask technology for ArF contact hole imaging for sub-100nm contact imaging. The author's activities have been focused on the design, fabrication and integration of imaging technology. In this paper the author's emphasis will be on issues related to pattern layout, mask fabrication and image processing.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CPL) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. These new reticle technologies have many issues that are similar to simple binary masks. The authors have investigated the printability of defects in CPL mask technology. Programmed defects of various sizes and types have been simulated and printed for sub 100nm imaging. High resolution scanning electron microscopy has been used to characterize these defects and develop an understanding of size and type that prints. In this paper the authors will focus on image line end shortening and the impact of through dose and focus performance for very high NA ArF imaging. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. Various types of line ends have been evaluated for either straight CPL mask or hybrid type builds.
As IC fabrication processes are maturing for the 130nm node, IC devices manufacturers are focusing on 90nm device manufacturing at ever-lower k1 values. Driven by cost savings, many integrated device manufacturers (IDMs) and foundries are working toward patterning critical mask layers of 90nm designs using high numerical aperture KrF exposure tools. The goal of this study is to find out whether KrF can be successfully used instead of ArF for fabricating 90nm devices. This exercise will help to gain learning for the upcoming 65nm node, where the early manufacturing phase will also be carried out at a similar k1 of near 0.3 using ArF. For high volume wafer production, the cost and throughput are in favor of using a single exposure PSM technique vs. the two masks and double exposure technique required for alternating phase shift masks (altPSM). The high mask cost of altPSM also discourages its use for low volume manufacturing. The two leading candidates candidates for 90nm node using KrF are: 6% attenuated PSM and CPL Technology. In this work, we present a methodology on how to use transmission tuning to achieve the best process latitude for patterning poly gate layer. First, we analyze the diffraction patterns from 6% attPSM and CPL mask features and identify the optimum transmission for various pitches. Next we describe how CPL mask can be used as a variable transmission attenuated mask to produce the best through pitch imaging performance and show a practical implementation method for applying to real device designs. Then we demonstrate how to integrate the optimized transmission tuning into the data process and OPC flow for generating CPL mask. Finally, we provide an example experimental result on a real device pattern.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometries has forced device manufacturers to k1’s approaching 0.40. In this paper the authors will focus on the impact of mask exposure error factor (MEEF) through pitch for 120nm contacts with and without assist features. Experimental results show that although the addition of scatter bars improves depth of focus it has a negative effect on MEEF.
The 65nm device generation will require steady improvements in lithography scanners, resists, reticles and OPC technology. 193nm high NA scanners and illumination can provide the desired dense feature resolution, but achieving the stringent overall 65nm logic product requirements necessitates a more coherent strategy of reticle, process, OPC, and design methods than was required for previous generations. This required integrated patterning solution strategy will have a fundamental impact on the relationship between design and process functions at the 65nm device node.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.
Despite very intense work since its re-discovery in the early 1990’s, phase-shift lithography is only in limited use today. The reason for its lack of wide spread use is not performance, for the benefits of phase-shift lithography are very well documented in the literature. The problem has been the greater complexity involved in making phase shirt masks, the inspection and repair of defects, and in dealing with phase-shift conflicts and other layout problems. The phase shift approach most commonly used is attenuated phase-shift. This is not very surprising in view of the fact that this phase-shift approach requires only one write-pass; and the inspection, repair and OPC are less difficult than the other phase-shift options. Despite these shortcomings, work on phase shift continues as we push resolution and extend the life of optical microlithography. The reason is that the alternatives, 157 nm and next-generation lithography, have its own set of issues. As we come to grips with the complexities of working in the vacuum region of the spectrum, we realize that 157 nm is likely to be delayed, and more expensive than originally thought. All next generation lithography options require a great deal of new infrastructure, with it associated coast. In this paper we report on a self-aligned rim phase shift approach. There have been reports of self-aligned rim phase shift approaches before, however our approach is unique in that it only requires one write-pass. This significantly simplifies the mask-making process.
We have demonstrated the fabrication of working 130 nm-node SRAMs with high yield using single layer ultra-thin resist (UTR) integrations. Transistor gates were fabricated using 140-nm-thick resist films in combination with a single layer, inorganic anti-reflective coating (ARC) that also acted as a hardmask (HM). An aggressive ARC/HM removal process was developed to enable the use of a thick ARC/HM. The thick ARC/HM was necessary to allow the incorporation of a resist trim step prior to polysilicon gate etch that reduced the transistor gate lengths in silicon from the printed critical dimension (CD) in resist. Transistor performance for both NMOS and PMOS devices with UTR-fabricated gates was equivalent to the performance of standard transistors. Working SRAM arrays were fabricated using UTR at the gate layer that achieved natural yield within 10% of the yield achieved with a thick resist process, and in some cases, with yield that exceeded the thick resist process. CD control for the UTR gate photo process was equivalent to the baseline photo process, and the UTR gate photo process was optimized to increase device yield. Contacts fabricated using 120-nm-thick resist films exhibited electrical characteristics equivalent to those fabricated with standard processes, and yielding SRAM devices were fabricated using UTR at the contact layer. Defect inspection of UTR contact patterning detected the formation of pinholes in the UTR films; however, the formation of pinholes was found to be dependent upon substrate-resist interactions.
The challenges of low k1 lithography require unique solutions at all levels of the lithography process. Chromeless phase lithography (CPL) is a promising technique that uses a 2-beam imaging strategy and a unique OPC application for enhanced CD uniformity through pitch. It is particularly effective when combined with a high numerical aperture (NA) and off-axis illumination (OAI). In addition to its imaging benefits, CPL masks offer many advantages in the manufacturing of the mask over other approaches.
The manufacturing strategy and methodology employed to fabricate CPL masks will be discussed. The technical challenges of mask production will also be highlighted. Application of CPL to production ArF images were characterized through simulations and experimental data demonstrating the capability of this technique to produce complex structures.
In this paper the concept of chromeless phase lithography (CPL) is introduced and experimental results on an ASML PAS 5500/800 are presented. CPL is a single exposure technique and is capable of resolution enhancement on all device layers (bright and dark field masks). Line space structures through pitch are measured with cross section and have O.35jim depth of focus (DOF) at 10% exposure latitude without forbidden pitches. CPL experimental results for a k1 of 0.38 (½ pitch) are presented for three DRAM device layers, isolation brick wall, storage capacitor, and honeycomb contact. Each of these layers have a DOF of O.35jim at 10% exposure latitude. CPL experimental results are presented for a SRAM gate and contact with lOOnm feature size (k1=O.32) and have a DOF of O.35jim at 10% exposure latitude.
Examining features of varying pitch imaged using phase-shifting masks shows a pitch dependence on the transmission best suited for optimum imaging. The reason for this deals with the relative magnitude of the zero and higher diffraction orders that are formed as the exposing wavelength passes through the plurality of zero and 180-degree phase-shifted regions. Subsequently, some of the diffraction orders are collected and projected to form the image of the object. Chromeless Phase-Shift Lithography (CPL) deals with using halftoning structures to manipulate these relative magnitudes of these diffraction orders to ultimately construct the desired projected image. A key feature of CPL is that with the ability to manipulate the diffraction orders, a single weak phase-shifting mask can be made to emulate any weak phase-shifting mask and therefore the optimal imaging condition of any pattern can be placed on a single mask regardless of the type of weak phase-shifter that produces that result. In addition, these structures are used to render the plurality of size, shape and pitch such that the formed images produce their respective desired size and shape with sufficient image process tolerance. These images are typically made under identical exposure conditions, but not limited to single exposure condition. These halftoning structures can be used exterior, as assist features, or interior to the primary feature. These structures can range in transmission from 0% to 100% and they can be phase-shifted relative to the primary features or not. Thus CPL deals with the design, layout, and utilization of transparent and semi-transparent phase-shift masks and their use in an integrated imaging solution of exposure tool, mask and the photoresist recording media. This paper describes the method of diffraction matching, provides an example and reviews some experimental data using high numerical aperture KrF exposure.
Low-k1 imaging, high-NA optics, pattern collapse, and the absorption of resist materials in 157-nm and EUV lithographies are driving down the thickness of the photoresist layer in integrated circuit fabrication processes. Although devices and test structures have been successfully fabricated with resist films thinner than 160 nm on various levels, the fabrication of working devices with high yield using ultrathin resist (UTR) integrations on multiple device layers has yet to be demonstrated. In the present work, gates have been patterned with 140-nm thick resist films with 10-15 defects per wafer, none of which are specific to the UTR process. Similar UTR gates were also patterned over 80-nm steps with no defects associated with the topography. The UTR NMOS transistors in this work have 10 pA/micrometers leakage and 400 (mu) A/micrometers drive currents, but the PMOS transistors do not perform as well. The line-edge roughness (LER) is 5-8 nm 3(sigma) depending upon exposure mask (binary vs. PSM) and substrate. Etching into 100 nm of crystalline Si reduces the LER to 4-7 nm 3(sigma) . The power spectral densities of the roughness have a Lorentzian shape, and most of the roughness occurs over length scales larger than 100 nm. Contact chains with electrical characteristics comparable to standard processes were fabricated with 120-nm thick resist films. Polysilicon as thick as 150 nm was etched successfully with 80-nm thick resist films and hardmasks.
Examining features of varying pitch imaged using phase- shifting masks shows a pitch dependence eon the transmission best suited for optimum imaging. The reason for this deals with the relative magnitude of the zero and higher diffraction orders that are formed as the exposing wavelength passes through the plurality of zero and higher diffraction orders that are formed as the exposing wavelength passes through the plurality of zero and 180- degree phase-shifted regions. Subsequently, some of the diffraction orders are collected and projected to form the image of the object. chromeless Phase-Shift Lithography (CPL) deals with using half-toning structures to manipulate these relative magnitudes of these diffraction orders to ultimately construct the desired projected image. A key feature of CPL is that with the ability to manipulate the diffraction orders, a single weak phase-shifting mask can be made to emulate any weak phase-shifting mask and therefore the optimal imaging condition of any pattern can be placed on a single mask regardless of the type of weak phase- shifter that produces that result. In addition, these structures are used to render the plurality of size, shape and pitch such that the formed images produce their respective desired size and shape with sufficient image process tolerance. These images are typically made under identical exposure conditions, but not limited to single exposure condition. These half toning structures can be used exterior, as assist features, or interior to the primary feature. These structures can range in transmission from 0 percent to 100 percent and they can be phase-shifted relative to the primary features or not. Thus CPL deals with the design, layout, and utilization of transparent and semi- transparent phase-shift masks and their use in an integrated imaging solution of exposure tool, mask and the photoresist recording media. This paper describes the method of diffraction matching, provides an example and reviews some experimental data using high numerical aperture KrF exposure.
Extreme ultraviolet lithography (EUVL), and possibly 157-nm lithography, will require thin imaging layers (< 1500 Angstroms). The leading EUV resist strategy utilizes thin resists based on materials designed for 248 nm wavelength exposure and hardmasks. This process has produced lines and spaces with reasonable linearity, resolution, photospeed, and line-edge roughness. Although previous work has approached these limits, integration of sub-150nm resists and hardmasks into current IC manufacturing process flows with acceptable defect control has not yet been demonstrated. The authors are investigating ultrathin resist processing for the gate and back end levels and have collected data on coating properties, defect density, etch selectivity, exposure latitude, and depth of focus. Key results include the demonstration of etching 1500 Angstroms of poly-Si with a 1200 Angstroms thick photoresist etch mask and the demonstration of via chain yield that is comparable to standard thickness resist processes.
Design and implementation of a multifunctional 'golden standard' wafer which facilitates easy and rapid measurement of the most important optical stepper parameters using commercially available metrology tools and software are described. In this design a stepped array of reference marks is permanently etched into a silicon oxide film on a silicon wafer. The most important feature of this method is that a permanently etched pattern is used as a reference standard, which may be used to compare a number of steppers over a period of time. When it is required to perform a distortion measurement the wafer is simply coated with photoresist and a series of full-field exposures are exposed on the stepper to be measured. Using this method, the errors due to individual stepper stages are removed since each lens distortion measurement is made with respect to a common grid pattern. Furthermore this method provides useful information regarding the accuracy of the stepper alignment system. In addition the permanent alignment marks on the wafer permit the measurement of individual stepper stage matching, as well as stage orthogonality errors.
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