In this work we present a cost-effective fabrication method for metal ring-shaped nanostructure arrays based on
nanosphere lithography. Periodic arrays of nanorings and nanocrescents were fabricated using a simple method that
includes self-assembled monolayer formation, plasma treatment and deposition of metal. Lower cost and higher
throughput were achieved due to the replacement of ion beam milling with reactive ion etching usually used in other
methods. The dimensions of ring-like structures could be controlled by the size of the polystyrene spheres, the amount of
deposited metal and the argon plasma etching time. These nanostructures can be made of essentially any metal and used
as elements in optoelectronic nanodevices.
We demonstrate a novel quantum dot based probe with inherent signal amplification upon interaction with a targeted proteolytic enzyme. This probe may be useful for imaging in cancer detection and diagnosis. In this system, quantum dots (QDs) are bound to gold nanoparticles (AuNPs) via a proteolytically-degradable peptide sequence to non-radiatively suppress luminescence. A 71% reduction in luminescence was achieved with conjugation of AuNPs to QDs. Peptide cleavage results in release of AuNPs and restores radiative QD photoluminescence. Initial studies observed a 52% rise in luminescence over 47 hours of exposure to 0.2 mg/mL collagenase. These probes can be customized for targeted degradation simply by changing the sequence of the peptide linker.
Ray-tracing is notorious of its computational requirement. There were a number of techniques to speed up the process. However, a famous statistic indicated that ray-object intersections occupies over 95% of the total image generation time. Thus, it is most beneficial to work on this bottle-neck. There were a number of ray-object intersection reduction techniques and they could be classified into three major categories: bounding volume hierarchies, space subdivision, and directional subdivision. This paper introduces a technique falling into the third category. To further speed up the process, it takes advantages of hierarchy by adopting a MX-CIF quadtree in the image space. This special kind of quadtree provides simple objects allocation and ease of implementation. The text also included a theoretical proof of the expected performance. For ray-polygon comparison, the technique reduces the order of complexity from linear to square-root, O(n) -> O(2(root)n). Experiments with various shape, size and complexity were conducted to verify the expectation. Results shown that computational improvement grew with the complexity of the sceneries. The experimental improvement was more than 90% and it agreed with the theoretical value when the number of polygons exceeded 3000. The more complex was the scene, the more efficient was the acceleration. The algorithm described was implemented in the polygonal level, however, it could be easily enhanced and extended to the object or higher levels.
The hardware implementation of fixed-point multiplication has become a standard feature in almost all processors and computing systems. Though many researchers have studied various multiplication techniques for ASIC technology, the same techniques may not yield the same performance for FPGA- based multipliers. In this paper, we investigate the costs and speed performances associated with various multiplication techniques implemented on a single XC4010PQ160-5 device. The investigation reveals the significant performance influencing factors for effective design of FPGA-based multipliers. Based on the understanding of the revealed performance influencing factors, we propose a parallel multiplication technique appropriate for FPGA implementations. The implementation results demonstrate that the proposed technique is valid and effective. This paper offers useful references for FPGA-based computing unit designs, and provides an important groundwork for effective design and development of FPGA-based computing systems.
The input images of Chinese characters are normally preprocessed using different image processing techniques before the main classification in the handwritten Chinese character recognition. The authors proposed a different approach to the system philosophy of solving the handwritten Chinese character recognition problem where no preprocessing is necessary. The Chinese characters are treated as ideographs. The proposed system consists of a Rough Classifier which trigger the different Fine Classifiers. Each classifier is an optimized artificial neural network using genetic algorithms. A reduced system has been implemented. The result shows that the proposed system has higher recognition rate than the similar systems reported and is more efficiency.
Geometry processing comprises of a great many computationally intensive floating-point operations. Real- time graphics systems generally use application-specific custom designed parallel hardware to provide the high performance computation power. When designing a graphics engine on a FPGA-based configurable computing system, cost- effectiveness is important. This paper investigates and proposes a cost-effective FPGA-based floating-point datapath for geometry process. It is designed to be a basic building block for FPGA-based geometry processors. The implemented datapath operates at a frequency of 6.25 Mhz and has an average floating-point operation time of 10.2 microseconds.
Handwritten Chinese character recognition system invariably sue different image processing techniques to preprocess the input image before the main classification and recognition techniques are used. The authors proposed a different approach to the system philosophy of solving the handwritten Chinese character recognition problem for no preprocessing is necessary. The Chinese characters are treat as ideographs. The proposed system comprise of a Rough Classifier which control the different Fine Classifiers. Each classifier is an optimized artificial neural network using genetic algorithms. A reduced system has been implemented. The result shows that the proposed system has higher recognition rate than the similar systems reported and is more efficiency.
A fast, simple and memory saving algorithm for stereogram generation is presented in this paper. It is a ray-tracing like algorithm making use of the cross-talk effect in stereoscopic computer graphics for generating single-image random-dot stereogram. It actively looks for the smallest equivalent class of points with the same color so that it gives the greatest freedom of coloring for artistic design with stereogram.
Driven by the excellent properties of FPGAs and the need for high-performance and flexible computing machines, interest in FPGA-based computing machines has increased dramatically. Fixed-point adders are essential building blocks of any computing systems. In this work, various high-speed addition algorithms are implemented in FPGAs devices, and their performance is evaluated with the objective of finding and developing the most appropriate addition algorithms for implementing in FPGAs, and laying the ground-work for evaluating and constructing FPGA-based computing machines. The results demonstrate that the performance of adders built with the FPGAs dedicated carry logic combined with some other addition algorithms will be greatly improved, especially for larger adders.
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