This paper describes the joint development and optimization of an advanced critical dimension (CD) control methodology at IBM’s 300 mm semiconductor facility. The work is initially based on 22 nm critical level gate CD control, but the methodology is designed to support both the lithography equipment (1.35 NA scanners) and processes for 22, 20, 18, and 14 nm node applications. Specifically, this paper describes the CD uniformity of processes with and without enhanced CD control applied. The control methodology is differentiated from prior approaches1 by combining independent process tool compensations into an overall CD dose correction signature to be applied by the exposure tool. In addition, initial investigations of product specific focus characterization and correction are also described.
Requirements for ever tightening overlay control are driving improvements in tool set up and matching procedures, APC
processes, and wafer alignment techniques in an attempt to address both systematic and non systematic sources of
overlay error. Thermal processes used in semiconductor manufacturing have been shown to have drastic and
unpredictable impacts on lithography overlay control. Traditional linear alignment can accommodate symmetric and
linearly uniform wafer distortions even if these defects vary in magnitude wafer to wafer. However linear alignment
cannot accommodate asymmetric wafer distortions caused by variations in film stresses and rapid thermal processes.
Overlay improvement techniques such as Corrections per Exposure can be used to compensate for known systematic
errors. However, systematic corrections applied on a lot by lot basis cannot account for variations in wafer to wafer grid
distortions caused by semiconductor processing. With High Order Wafer Alignment, the sample size of wafer alignment
data is significantly increased and modeled to correct for process induced grid distortions. HOWA grid corrections are
calculated and applied for each wafer. Improved wafer to wafer overlay performance was demonstrated.
How HOWA corrections propagate level to level in a typical alignment tree as well as the interaction of mixing and
matching high order wafer alignment with traditional linear alignment used on less overlay critical levels. This
evaluation included the evaluating the impact of overlay offsets added by systematic tool matching corrections, product
specific corrections per exposure and 10 term APC process control.
Traditional scanner matching methods have been based in 1D proximity matching targets
and the use of wafer-based CD metrology to characterize both the initial mismatch as
well as the sensitivity of CDs to scanner tuning knobs.
One such method is implemented in ASML Pattern Matcher, which performs a linear
optimization based on user provided CD sensitivities and pre-match data. The user
provided data usually comes from wafer exposures done at multiple scanner illumination
conditions measured with CD-SEM. In the near future ASML plans to provide the
capability to support YieldStar CD data for Pattern Matcher which will collect CD data
with higher precision and much faster turn-around-time that CD-SEM.
Pattern Matcher has been used successfully in multiple occasions. Results for one such
occasion are shown in Figure 1 which presents the through pitch mismatch behavior of
one ASML XT:1400F with respect to an ASML XT:1400E for a 32nm contact layer.
Silicon Technology Development for the ITRS 65nm-node is in the final stage of an intense 2-year cycle with the full-entitlement technology qualification by the end of 2005. Accordingly, reticle technology development in support of the 65nm-node has advanced a great deal since the initial efforts began several years ago. One of the most challenging aspects of 65nm-node mask technology development is the mask inspection, which is also the main cost-driver for the 65nm-node reticle technology. As a result, controlling 65nm-node reticle cost via leveraging advanced mask inspection technologies has become a leading factor in enabling prolonged success of the 65-nm node technology for years to come. With this paper, we report our closing work on reticle inspection capability development for the 65nm-node process technology development cycle for a full-volume production ramp.
Among the valid gate pattern strategies for the 65nm technology node, att-PSM offers the advantage in cost and mask complexity over other contenders such as complimentary alt-PSM and chromeless phase lithography (CPL). A combination of Quasar illumination and sub-resolution assist features (SRAFs) provides a through pitch solution with a common depth of focus (DOF) better than 0.25um to support the aggressive scaling in both logic and high density SRAM. A global mask-source optimization scheme is adopted to explore the multi-dimensional space of process parameters and define the best overall solution that includes scanner optics such as NA and illumination, and SRAF placement rules for 1-dimensional line and space patterns through the full pitch range. Gate pattern capabilities in terms of DOF, exposure latitude, mask error enhancement factor (MEEF), optical proximity correction (OPC), CD control, and aberration sensitivity are reported in this paper. Conflict resolution and placement optimization are key to the success of implementation of SRAF to the complex 2-dimensional layouts of random logic. Reasonable CD control can be achieved based on the characterization and simulation of CD variations at different spatial and processing domains from local to across chip, across wafer, wafer-to-wafer, and lot-to-lot. Certain layout restrictions are needed for high performance devices which require a much tighter gate CD distribution. Scanner optimization and enhancement such as DoseMapper are key enablers for such aggressive CD control. The benefits, challenges, and possible extensions of this particular approach are discussed in comparison with other techniques.
Spectra of contact hole arrays with target diameters ranging from 106 to 131 nm and pattern pitch ranging from 220 to 300 nm are taken from an off-axis (65°) rotating compensator spectroscopic ellipsometry (RCSE).[1] 3-dimensional finite difference (FD3D) model developed by H. Chu,[2] is applied in the studies. To ensure accuracy of optical dispersion of each film, the simultaneous use of angle resolved beam profile reflectometry (BPR), broadband spectroscopic reflectometry (BB), and SE of an Opti-Probe 7341 are used for characterizing of the resist and BARC films. In particular, The extracted n&k dispersions are used to model the contact hole SE data using Therma-Wave's proprietary 3-dimensional RT/CD technology.[3,4] The performance of stability of both static and dynamic repeatability, uniformity, and correlation to other independent technology (i.e., SEM) will be presented in this paper.
The slow progress of the 157nm-F2 laser exposure tool development results in broad adaptation of high numerical aperture (NA>0.8) 193nm-ArF lithography for the 65nm-node production solution. This decision, however, forces lithographers to increase dependency on very aggressive RET technologies. This in turn demands mask making capabilities the industry has never faced before such as 100nm (@4X on mask scale) size Sub Resolution Assist Features (SRAF). This report covers our early work on our mask making capability development for the 65nm-node process technology development cycle for production in 2005. Our report includes the 65nm node mask technology capability development status for mask CD and registration dimensions control, current inspection capability/issues and development efforts for critical layer masks with aggressive RET (especially of EAPSM with SRAF).
Won Kim, Shinji Akima, Christopher Aquino, Charika Becker, Mark Eickhoff, Tsuyoshi Narita, Soo-Kim Quah, Peter Rohr, Robert Schlaffer, Junichi Tanzawa, Yoshiro Yamada
As our chip producing industry rapidly ramps to mass production of the 130nm device technology node and wrapping up the final stages of 90nm node process technology development, the ability to inspect all types of 130nm node masks and early identification of shortcomings in 90nm node mask inspection are extremely important.
In this paper, we share our experience of mask inspection for the 90nm and 130nm nodes, using the advanced TeraStar mask inspection system (KLA-Tencor) with the SEMI programmed defect standard masks, comprising three substrate types (binary, 248nm-KrF MoSi and 193nm-ArF MoSiON). Both Die-to-Die (D2D) and Die-to-Database (DDB) inspections were carried out and the results are presented with our assessments of benefits and shortcomings of those methods. To verify the resulting defects actually impact device functionality, we also carried out systematic printability experiments with our proprietary 130nm and 90nm nodes lithography processes. The wafer results were then compared with mask inspection results and mask measurement data to draw our final conclusions. In addition, we will also present inspection performance of the TeraStar system on our 130nm production masks and very challenging 90nm node (ArF EAPSM/AAPSM) development masks.
Mask critical dimension (CD) control relies on advanced write tools and resist processes. However, a specified write tool and process does not necessarily guarantee high mask quality. As the mask feature size shrinks to below 500 nm, there are other mask-related factors that can also significantly affect the mask performance. This paper discusses the impact of those non-trivial factors, such as mask writing tool and process control, calibration of mask CD metrology, blank quality of attenuated phase shift mask (ATPSM), pellicle degradation due to 193 nm laser irradiation, and profile of mask features, etc.
This paper presents a methodology for modeling the space printability at the gate level in 193nm lithography. Spaces are shown to be more susceptible to process variations and lens aberrations than lines are. Experimental Scanning Electron Microscopy (SEM) pictures show that the scum and bridging effects can occur in spaces although all the line critical dimensions (CDs) are on target. A resist imaging model is used to simulate the line CDs through defocus, pitch and size, and the prediction error is within 5nm. However, this model can not reasonably predict space CDs without using variable threshold, which is explained a proposed trajectory dissolution rate model. Based on the dissolution model, a process rule checker is proposed which inspects the peak light intensity in a space and compares it with a given threshold. This condition is verified experimentally.
As our chip producing industry gearing up for mass production of 130nm device technology node, use of EAPSM (Embedded Attenuated Phase Shift Mask) technology in the critical pattern levels became unavoidable because of the low k1 factor lithography involved. However, this 2-layer EAPSM material (attenuator material covered with Chrome) requires two distinctively separate lithography/etch processes needed to be carried out. These added complexities of processes are prone to degradation of the absorber material's (MoSi) sidewall leading to imperfect sidewall profiles (top corner rounding, off-normal sidewall angle, etching intrusion into quartz substrate, footing, . . . etc.). These imperfections of sidewall cause aerial image degradations thus reduce effectiveness of full benefits of PSM technology. In this paper, we discuss our findings of mask level aerial image degradation dependency on EAPSM material sidewall imperfections, which result from immature mask making processes, and assessments of its effects on pattern transfer onto wafer level using 3&2D EMF and subsequent lithography simulations. The results were then, compared to actual wafer results for the wafer level printing confirmation to the simulation results. We distinguish consequence of resulting aerial image differences between EMF simulations vs. Kirchhoff approximation (treatment of absorber to be infinitely thin layer; normally used in conventional lithography simulations) in the KrF EAPSM material (MoSi). Furthermore, we have carried out look-ahead assessments for ArF (193nm) lithography using ArF EAPSM material (MoSiON) and made association between the sidewall profile variations and CD uniformity performance of EAPSM. We will make case that 3D EMF capability consideration is important in the low k1 factor lithography simulations.
As the chip making industry gearing up for mass production of 130nm device technology node, Critical Dimension (CD) control becomes ever more important. Among many sources of possible contributions, there is increasing trend that the contributions are being identified for mask making processes itself. For example, at 180nm node, mask contribution to CD control has been 40~45 percent while at 250nm node the contribution was < 20 percent. At 130nm node, it is expected that mask contribution to CD non-uniformity could reach > 60 percent if existing mask making processes are continue to be employed. 60~70 percent of CD non-uniformity contribution from mask is clearly not acceptable. Therefore, we have engaged with our mask suppliers to bring in 50-kV e-beam vector mask pattern generator and dry etch process quickly for critical levels of 130nm device technology node production ramp. In this paper, we will share wafer FAB experiences of quickly implementing the 50-kV vector e-beam pattern generator and dry etch process for 130nm device node ramp. We will be discussing benefits realized from this transition in terms of; mask and wafer pattern fidelity improvements, mask CD linearity Improvements, e-beam writer process resist tone effects, finally and most importantly, impact on the wafer level CD control; Across the Chip Linewidth Variation (ACLV) reductions.
ArF lithography is pushing its limit to beyond the 100-nm node due to delay of NGL technologies to meet the aggressive insertion schedules. However, lithography process for 100-nm node with binary mask and ArF resist is still not easy to achieve and will be one of the big challenges for lithography community. Although there have been significant improvements over the past year, ArF resists remain as the most critical aspect in ArF lithography development. Areas of concern for ArF resist include; higher level of environmental instability compared to KrF materials, different response depending on the tone of reticles, and different performance exhibited between microsteppers used for initial development and full field scanners to be used in manufacturing. We expect that these problems will be getting worse in sub 100-nm node. To achieve the most challenging performance goals, the resist to be used in manufacturing will require optimization of the chemical formulation of commercialized resists based on specific design requirements, process and environmental conditions. This paper will describe an extensive DOE (design of experiments) that was performed in order to find better resist formulation from commercialized resists for our specific FAB environment. PAG, resin and amine were main three components for this DOE. After choosing the best resist for 100-nm node, we have will evaluated actual lithographic performance capability such as DOF, exposure latitude, etc.
157nm lithography is expected to be the lithography choice for the 100nm-technology node, which is scheduled to be in full-production in 2003. However, due to 157nm photons being strongly absorbed by commonly used polymeric organic materials, a completely new class of material (containing F and Si-O) will be needed for 157nm Single Layer Resist (SLR) system. It is expected that the 157nm SLR system development will take greater than 3 years, which the industry will barely have, until the projected 2003 production schedule. In an attempt to fill the gap and to provide working resist system, using thin (<100nm)films of existing resist materials along with inorganic thin hardmask/BARC films is an attractive approach. In this paper, we report the optical constants (n % k at 157nm as well as 193nm and 248nm) of various thin film hardmask/BARC candidate materials (SixNyHz, SixOyNz, SixCyCVD and TixNyPVD films) measured by VUV-VASE. The films' atomic compositions, determined by RBS/HFS, were varied by controlling feed gas flow rates in order to vary the optical behavior. However, we limited our study within the low process temperature PE-CVD and PVC films due to our intention of using these films along with LowK(2.7approximately equals 2.0) dielectric materials. In addition, we will also report the optical constants of two types of LowK materials (PE-CVD OSG film and Spin- On/Cure low-density organosilicate dielectrics by JSR.) The data is, then, used to optimize the physical properties (n & k) and utilized to determine suitable hardmask/BARC material for 157nm exposure using Prolith II simulation. The results containing property of these hardmask/BARC candidate films and our optimization analysis along with the first successful pattern transfer feasibility demonstration into realistic substrate material (poly-Si) using ultra thin resist (currently existing) at 157nm optical lithography are reported.
Two lithography strategies - of alternating PSM using double expose method (DEM) and high transmission attenuated PSM - were investigated to assess their capability for printing 0.1 micrometers gate. In order to do that, the optimization of each process has been carried out for maximizing the process window; of depth of focus (DOF) and expose latitude (EL), to make them satisfy process requirement generated by focus and expose budget study. The key components of optimization are finding the best NA and sigma, the optimum bias for isolated lines and dense lines and the optimum transmission of att PSM. Then, the impacts of some critical lithographic parameters such as phase error effects in APSM, proximity effects and mask error factor (MEF) were determined with experimental data. As final answer to the question of process capability of two lithography techniques for 0.1 micrometers gate patterning, CD control analysis was made to see if they satisfy our gate CD control requirements.
Thin Layer Imaging (TLI) technique offers opportunity for lithographic performance gain as well as issues relating to its complexity of the process. Of those improvement possibilities, utilizing hyper fine resolution one can gain using very thin (<250 nm) imaging layer, has been a gateway to access the otherwise unavailable sub-wavelength features using the currently available exposure tools. However, pattern transfer from the imaging layer (wet developed) to the main etch resistance layer (organic bottom layer also act as BARC, Bottom Anti Refractive Coat, during exposure) requires considerable efforts in bottom layer dry-develop etch process optimization on a plasma etch chamber. And, such an extra process requires significant amount of engineering attention to the multi layer process scheme. In this paper, we report the 140 nm (k1 equals 0.44, including true dense, 1:1 arrays) contact hole printing results (lithographic performance including resolution, focus/exposure latitudes, proximity effects) using standard binary chrome-on-quartz mask as well as the subsequent pattern transfer process optimization. The lithographic exposure was performed on a 10X ISI microstepper operating at 193 nm ArF laser source located at the RTC (Resist Test Center) of the International Sematech. The dry development DOE experiments were performed on a LAM TCP9400PTX inductively coupled plasma (ICP) etch chamber also residing at the RTC. The effect of process conditions (TCP power, bias power, O2/SO2 gas flow/ratio, and chamber pressure and chuck temperature) on the integrity of pattern transfer (etch rate, selectivity, CD bias, side wall profile) were investigated by full factor designed experiments.
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