Block copolymer (BCP) directed self-assembly (DSA) is a promising extension of optical
lithography for patterning irregularly positioned contact holes of integrated circuits. The small
topographical templates are shown to guide the self-assembly off the natural geometry by strong
boundary confinement [1-2], and has been demonstrated to pattern 22nm random logic circuits using
[2-3]. Here we present a general template design strategy that relates the DSA material properties to
the target technology node requirements and experimentally demonstrated DSA contact hole
patterning for half adders at the 14 nm and 10 nm nodes.
Block copolymer directed self-assembly (DSA) is a promising extension of optical lithography
for device fabrication akin to double-patterning. The irregular distribution of contact holes in circuit
layouts is one of the biggest challenges for DSA patterning because the self-assembly tends to form
regular patterns naturally. Although the small guiding templates are shown to guide the
self-assembly off the natural geometry by strong boundary confinement [1, 2] (Fig. 1), it is
insufficient to simply surround contact holes with guiding templates without optimizing the
placement and geometry of the guiding templates.
The use of block copolymer self-assembly for device fabrication in the semiconductor industry
has been envisioned for over a decade. Early works by the groups of Hawker, Russell, and Nealey
[1-2] have shown a high degree of dimensional control of the self-assembled features over large
areas with high degree of ordering. The exquisite dimensional control at nanometer-scale feature
sizes is one of the most attractive properties of block copolymer self-assembly. At the same time,
device and circuit fabrication for the semiconductor industry requires accurate placement of desired
features at irregular positions on the chip. The need to coax the self-assembled features into circuit
layout friendly location is a roadblock for introducing self-assembly into semiconductor
manufacturing. Directed self-assembly (DSA) and the use of topography to direct the self-assembly
(graphoepitaxy) have shown great promise in solving the placement problem [3-4]. In this paper, we
review recent progress in using block copolymer directed self-assembly for patterning sub-20 nm
contact holes for practical circuits.
State of art III-V multi-junction solar cells have demonstrated a record high efficiency of 43.5%. However, these cells
are only applicable to high concentration systems due to their high cost of substrates and epitaxial growth. We
demonstrate thin film flexible nanostructure arrays for III-V solar cell applications. Such nanostructure arrays allow
substrate recycling and much thinner epitaxial layer thus could significantly reduce the cost of traditional III-V solar
cells. We fabricate the GaAs thin film nanostructure arrays by conformally growing GaAs thin film on nanostructured
template followed by epitaxial lift-off. We demonstrate broadband optical absorption enhancement of a film of GaAs
nanostructure arrays over a planar thin film with equal thickness. The absorption enhancement is about 300% at long
wavelengths due to significant light trapping effect and about 30% at short wavelengths due to antireflection effect from
tapered geometry. Optical simulation shows the physical mechanisms of the absorption enhancement. Using thin film
nanostructure arrays, the III-V solar system cost could be greatly reduced, leading to low $/W and high kW/kg flexible
solar systems.
In many ways, sidewall spacer double patterning has created a new paradigm for lithographic roadmaps. Instead of
using lithography as the principal process for generating device features, the role of lithography becomes to generate a
mandrel (a pre-pattern) off-of-which one will subsequently replicate patterns with various degrees of density
multiplication. Under this new paradigm, the innovativeness of various density multiplication techniques is as critical to
the scaling roadmap as the exposure tools themselves.
Sidewall spacer double patterning was the first incarnation of mandrel based patterning; adopted quickly in NAND flash
where layouts were simple and design space was focused. But today, the use of advanced automated decomposition
tools are showing spacer based patterning solutions for very complex logic designs. Future incarnations can involve the
use of laminated spacers to create quadruple patterning or by retaining the original mandrel as a method to obtain triple
patterning. Directed self-assembly is yet another emerging embodiment of mandrel based patterning, where selfseparating
polymers are registered and guided by the physical constraint of a mandrel or by chemical pre-pattern trails
formed onto the substrate.
In this summary of several bodies of work, we will review several wafer level demonstrations, all of which use various
forms of mandrel or stencil based density multiplication including sidewall spacer based double, triple and quadruple
patterning techniques for lines, SADP for via multiplication, and some directed self-assembly results all capable of
addressing 15nm technology node requirements and below. To address concerns surrounding spacer double patterning
design restrictions, we show collaboration results with an EDA partner to demonstrate SADP capability for BEOL
routing layers. To show the ultimate realization of SADP, we partner with IMEC on multiple demonstrations of
EUV+SADP.
Single FETs and CMOS inverters with 20 nm contact holes patterned using self-assembled diblock copolymer are
demonstrated in this work. Alignment of the self-assembled contact holes to the MOSFET source and drain is achieved
with a unique guiding layer and the self-assembly process is integrated with an existing CMOS process flow using
conventional tools on a full 4" wafer level. Potential application for block copolymer patterning on SRAM circuit level is
also discussed.
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