Patterning of contact hole using KrF lithography system for the sub 90nm technology node is one of the most
challenging tasks. Contact hole pattern can be printed using Off-Axis Illumination(OAI) such as dipole or Quasar or
Quadrupole at KrF lithography system. However this condition usually offer poor image contrast and poor Depth Of
Focus(DOF), especially isolated contact hole. Sub-resolution assist features (SRAF) have been shown to provide
significant process window enhancement and across chip CD variation reduction. The insertion of SRAF in a contact
design is mostly done using rule based scripting. However the rule based SRAF strategy that has been followed
historically is not always able to increase the process window of these 'forbidden pitches' sufficiently to allow
sustainable manufacturing. Especially in case of random contact hole, rule-based SRAF placement is almost impossible
task. We have used an inverse lithography technique to treat random contact hole.
In this paper we proved the impact of SRAF configuration. Inverse lithography technique was successfully used to treat
random contact holes. It is also shown that the experimental data are easily predicted by calibrating aerial image
simulation results. Finally, a methodology for optimizing SRAF rules using inverse lithography technology is described.
As a conclusion, we suggest methodology to set up optimum SRAF configuration with rule and inverse lithography
technology.
Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm
technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI)
such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus
(DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an
important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image
contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated
features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a
contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are
derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of
assist features to be used. However in the case of random contact holes, rule-based SRAF placement is a nearly
impossible task.
To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The
impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also
shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a
methodology for optimizing SRAF rules using inverse lithography technology is described.
Design For Manufacturing (DFM) has become an important focusing part in the semiconductor
industry as the feature size on the chip goes down below the 0.13um technology. Lots of DFM related ideas
have been come up, tried, and adopted for wider process window and higher device performance. As the
minimum features are getting shrunk, the design rules also become more complicated, but still not good
enough to describe the certain pattern that imposes narrow process window or even failure of device. Thus,
these process hot spot patterns become to identify, correct, or remove at the design step. One of the efforts is
to support a DFM guide line to the designer or add to conventional DRC rules. However it is very difficult to
make DFM guideline because we detect the hot spot pattern and confirm if these patterns is real hot spot or
not.
In this study, we developed effective methodology how to make DFM guide line. Firstly we use the s
oftware, called nanoscope to detect hot spots on post OPC layouts and then make this detected hot spot patter
n to test patterns that it can check electrical performance and then we compared with electrical performance a
ccording to split condition. It is confirmed this method is very effective to make DFM guide line below the 0.
13um technology.
Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm
technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI)
such as Quasar or Quadrupole. However, such a source usually offers poor image contrast and poor depth of focus
(DOF), especially for isolated contact holes. In addition to image contrast and DOF, circularity of hole shape is also an
important parameter for device performance. Sub-resolution assist features (SRAF) can be used to improve the image
contrast, DOF and circularity for isolated contact holes. Application of SRAFs, modifies the intensity profile of isolated
features to be more like dense ones, improving the focal response of the isolated feature. The insertion of SRAFs in a
contact design is most commonly done using rule-based scripting, where the initial rules for configuring the SRAFs are
derived using a simulation tool to determining the distance of assist features to main feature, and the size and number of
assist features to be used.. However in the case of random contact holes, rule-based SRAF placement is a nearly
impossible task.
To address this problem, an inverse lithography technique was successfully used to treat random contact holes. The
impact of SRAF configuration on pattern profile, especially circularity and process margin, is demonstrated. It is also
shown that the experimental data are easily predicted by calibrating aerial image simulation results. Finally, a
methodology for optimizing SRAF rules using inverse lithography technology is described.
It has been widely accepted that to ensure good yield in IC wafer manufacturing, early adaptation of DFM (Design for
Manufacturability) guidelines in design phase is required and it is particularly true in Foundry business. Integrated
foundry approaches for DFM guideline development were presented in this paper. With emphasis of process variations
and process sensitivity impact on design patterns, we describe the procedure of the combination of rule-based and
simulation-based lithographical hotspot pattern characterizations. An evaluation of process sensitivity metrics for
analyzing potential pattern hotspots is then described. In addition, based on hotspot pattern severity, repeated patterns
from different designs are saved into a pattern library as knowledge deposition tool and those patterns can be easily
identified later in new designs through pattern search, which is much faster than simulation based hotspot detections.
With this approach, a set of DFM compliance rules is derived to designs in the design implementation stage for both
110nm and 90nm technology nodes, striving to gain more yield, device performance, and improve time-to-volume
production.
Foundry companies encounter again and again the same or similar lithography unfriendly patterns (Hot-spots) in
different designs within the same technology node and across different technology nodes, which eluded design rule
check (DRC), but detected again and again in OPC verification step. Since Model-based OPC tool applies OPC on
whole-chip design basis, individual hot-spot patterns are treated same as the rest of design patterns, regardless of its
severity.
We have developed a methodology to detect those frequently appeared hot-spots in pre-OPC design, as well as post
OPC designs to separate them from the rest of designs, which provide the opportunity to treat them differently in early
OPC flow. The methodology utilizes the combination of rule based and pattern based detection algorithms. Some hotspot
patterns can be detected using rule-based algorithm, which offer the flexibility of detecting similar patterns within
pre-defined ranges. However, not all patterns can be detected (or defined) by rules. Thus, a pattern-based approach is
developed using defect pattern library concept. The GDS/OASIS format hot-spot patterns can be saved into a defect
pattern library. Fast pattern matching algorithm is used to detect hot-spot patterns in a design using the library as a
pattern template database. Even though the pattern matching approach lacks the flexibility to detect patterns' similarity,
but it has the capability to detect any patterns as long as a template exists. The pattern-matching algorithm can be either
exact match or a fuzzy match. The rule based and pattern based hot-spot pattern detection algorithms complement each
other and offer both speed and flexibility in hot spot pattern detection in pre-OPC and post-OPC designs.
In this paper, we will demonstrate the methodology in our OPC flow and the benefits of such methodology application
in production environment for 90nm designs. After the hot spot pattern detection, examples of special treatment to
selected hot spot patterns will be shown.
Flare has become a significant problem for low K1 lithography process.[1] It is generally divided into three parts:
long-, local-, short-range. Long-range flare is scattering over a scale of tens of microns, come from reflections within the
projection lens. Short-range is scattering over a scale of about 1 micron or less, come from lens aberrations. And localrange
flare is scattering over about 1 to 10 microns, comes from inhomogenieties within glass and local pattern density.
Especially, local-range flare causes the printed width to vary or degrade printing accuracy. Normally, the local-range
flare effect is increase by local pattern density. Therefore the local flare effect can be reduced if the effect of local pattern
density within die is compensated effectively.
In this paper, we discussed full chip compensation for local flare effect using OPC/DRC method. First of all, we
investigated relationship between local flare and pattern density using test pattern and extracted OPC model according
to pattern density and also analyzed within chip pattern density distribution using DRC. We separated original layout to
OPC target layout according to local pattern density, applied different OPC model to each separated layout. We will
show within chip CD variation was improved after local flare effects reduction.
Design For Manufacturing (DFM) has been paid attention as the feature size on chip goes down below the k1 factor of
0.25. Lots of DFM related ideas have been come up, tried, and some of them adopted for wider process window and as a
result, higher yield. As the minimum features are getting shrunk, the design rules become more complicated, but still not
good enough to describe the complexity and limitation of certain patterns that imposes narrow process window, or even
failure of device. Thus, it becomes essential to identify, correct, or remove the litho-unfriendly patterns (more widely
called as hot spots), before OPC. One of the efforts is to write a DFM rules in addition to conventional DRC rules.
In this study, we use the software, called YAM (Yield Analysis Module) to detect hot spots on pre-OPC layouts.
Conventional DRC-based search is not able to surpass YAM, as it enables to identify hot spots in either much easier way
or even ones that are unable to be found by DRC. We have developed a sophisticated methodology to detect and fix
OPC- and/or litho-unfriendly patterns. It is confirmed to enlarge process window and the degree of freedom on OPC
work.
For the 90nm node and beyond, smaller Critical Dimension(CD) control budget is required and the ways to control good
CD uniformity are needed. Moreover Optical Proximity Correction(OPC) for the sub-90nm node demands more accurate
wafer CD data in order to improve accuracy of OPC model. Scanning Electron Microscope (SEM) is the typical method
for measuring CD until ArF process. However SEM can give serious attack such as shrinkage of Photo Resist(PR) by
burning of weak chemical structure of ArF PR due to high energy electron beam. In fact about 5nm CD narrowing occur
when we measure CD by using CD-SEM in ArF photo process. Optical CD Metrology(OCD) and Atomic Force
Microscopy(AFM) has been considered to the method for measuring CD without attack of organic materials. Also the
OCD and AFM measurement system have the merits of speed, easiness and accurate data. For model-based OPC, the
model is generated using CD data of test patterns transferred onto the wafer. In this study we discuss to generate accurate
OPC model using OCD and AFM measurement system.
KEYWORDS: Data modeling, Optical proximity correction, Data conversion, Process modeling, Critical dimension metrology, Reactive ion etching, Scanning electron microscopy, Photomasks, Etching, Image processing
OPC has become an indispensable tool used in deep sub-wavelength lithograph process enabling highly accurate CD
(Critical Dimension) control as design rule shrinks. Rule based OPC was widely acceptable in the past, however it has
recently turned toward model OPC according to the decreasing pattern size. Model based correction was first applied to
the optical proximity phenomenon because the image of sub-wavelength pattern is distorted severely during the optical
image transformation. In addition, more tight CD control required to compensate the process induced error effects from
etch or other process as well optical image can be achieved.
In this paper, we propose advanced OPC method to obtain better accuracy on the final target for sub-90nm technology.
This advanced method converts measured CD data into final CD target by using an equation. We compared the results
from the data converting method, suggested in this paper, with those from post-litho(DI), post-etch (FI) OPC model step
by step. Finally we confirmed that advanced new OPC method gives better accuracy than that from conventional OPC
model
OPC(Optical Proximity Correction) has become an indispensable tool used in deep sub-wavelength lithograph process enabling highly accurate CD (Critical Dimension) control as design rule shrinks. Current model based OPC is a combination of optical and process model to predict lithography process. At this time, the accurate OPC model can be made by accurate empirical measurement data. Therefore empirical measurement data affects OPC model directly. In the case of gate layer, it affects to device performance significantly and CD spec is controlled tightly. Because gate layer is hanging on between active area and sti area, the gate CD is affected by different sub layer stack and step height. This paper will analyze that the effect of sub layer on the OPC model and show difference EPE value results at the patterns such as iso line, iso space,pitch, line end and T_junction between poly and gate model using constant threshold model.
The advanced lithography needs to be tightly controlled in various areas of lithography. The mask CD specification is one of new areas required much tighter control. Typically, mask CD error can be sorted as two different categories. One is Mean-to-target (MTT) and another is CD uniformity (CDU). The MTT is the difference between the target value and the average value of the measured CD on the mask. CDU means CD uniformity across mask. Those two potential errors can be magnified on the wafer level due to the MEEF. To overcome the MTT, we can adjust expose dose to compensate mask CD error so that we achieve targeted CD on the wafer level. However, the changing expose dose also induces process window change due to the MEEF. It means that we have narrower process window even if we get the targeted CD on the wafer level. On the other hand, CDU can give two different effects on the wafer level. One is narrower process window due to magnified ACLV (Across Chip Line-width Variation) due to the MEEF. Another effect of CDU is the poor OPC accuracy caused by different MEEF as function of pitch. For example, we assume that CD difference of dense line and isolated line is 10 nm on the mask. However, on the wafer, this 10 nm can be magnified as 20 nm by MEEF difference between two structures. Therefore, we think that the mask specification needs to take account those effects. In this paper, we will show technical data to prove how MTT and CDU impact on process window and OPC accuracy. And we will show how we have to make mask specification to overcome those effects.
Since an OPC engine makes model to fit wafer printed CD of OPC test mask to simulation CD of test pattern layout, the target CD of OPCed mask is not design CD but the CD of OPC test mask. So, the CD difference between OPC test mask and OPCed mask is one of the most important error source of OPC. We experimentally obtained OPC CD error of several patterns such as iso line, iso space, dense line, line end, effected by the mask MTT (mean to target) difference of the two masks on of 90nm logic pattern with an ArF attenuated mask having designed different MTT. The error is compared to simulated data that is calculated with MEEF (mask error enhancement factor) and EL (exposure latitude) data of these patterns. The good agreement of the experimental and calculated OPC error effected mask MTT error can make OPC error are predicted by mask CD error. Using by these calculation, we made mask CD window to meet OPC spec for 90nm ArF process.
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